mirror of
https://github.com/YosysHQ/yosys
synced 2026-04-26 13:53:34 +00:00
79 lines
1.2 KiB
Text
79 lines
1.2 KiB
Text
read_verilog <<EOT
|
|
module alu_sub_3op(
|
|
input [7:0] a, b, c,
|
|
output [7:0] y
|
|
);
|
|
assign y = a - b + c;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
alumacc
|
|
opt_clean
|
|
csa_tree
|
|
opt_clean
|
|
select -assert-count 2 t:$fa
|
|
select -assert-count 1 t:$add
|
|
select -assert-none t:$alu
|
|
select -assert-none t:$sub
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module alu_sub_mixed(
|
|
input [7:0] a, b, c, d,
|
|
output [7:0] y
|
|
);
|
|
assign y = a + b - c + d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
alumacc
|
|
opt_clean
|
|
csa_tree
|
|
opt_clean
|
|
select -assert-count 3 t:$fa
|
|
select -assert-count 1 t:$add
|
|
select -assert-none t:$alu
|
|
select -assert-none t:$sub
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module alu_sub_all(
|
|
input [7:0] a, b, c, d,
|
|
output [7:0] y
|
|
);
|
|
assign y = a - b - c - d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
alumacc
|
|
opt_clean
|
|
csa_tree
|
|
opt_clean
|
|
select -assert-count 3 t:$fa
|
|
select -assert-count 1 t:$add
|
|
select -assert-none t:$alu
|
|
select -assert-none t:$sub
|
|
design -reset
|
|
|
|
read_verilog <<EOT
|
|
module alu_sub_signed(
|
|
input signed [7:0] a, b, c, d,
|
|
output signed [9:0] y
|
|
);
|
|
assign y = a + b - c - d;
|
|
endmodule
|
|
EOT
|
|
hierarchy -auto-top
|
|
proc
|
|
alumacc
|
|
opt_clean
|
|
csa_tree
|
|
opt_clean
|
|
select -assert-count 3 t:$fa
|
|
select -assert-count 1 t:$add
|
|
select -assert-none t:$alu
|
|
select -assert-none t:$sub
|
|
design -reset
|