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Code Activity
yosys/tests/errors
History
Miodrag Milanovic 48a3dcc02a End of file fix
2026-06-23 07:23:41 +02:00
..
syntax_err01.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err02.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err03.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err04.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err05.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err06.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err07.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err08.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err09.v End of file fix 2026-06-23 07:23:41 +02:00
syntax_err10.v Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
syntax_err11.v Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
syntax_err12.v Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00
syntax_err13.v End of file fix 2026-06-23 07:23:41 +02:00