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yosys/techlibs/gowin
2026-06-25 08:49:02 +02:00
..
adc.v End of file fix 2026-06-23 07:23:41 +02:00
arith_map.v End of file fix 2026-06-23 07:23:41 +02:00
brams.txt GOWIN. Disable read-before-write mode. 2026-03-05 09:17:37 +10:00
brams_map.v gowin: Fix bram ADA byte enables 2026-02-22 09:00:37 +01:00
brams_map_gw5a.v gowin: Fix bram ADA byte enables 2026-02-22 09:00:37 +01:00
cells_latch.v gowin: add hardware latch support (DL/DLN/DLC/DLP variants) 2026-03-05 16:04:23 +01:00
cells_map.v iopadmap: Add native support for negative-polarity output enable. 2021-11-09 15:40:16 +01:00
cells_sim.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
cells_xtra.py End of file fix 2026-06-23 07:23:41 +02:00
cells_xtra_gw1n.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
cells_xtra_gw2a.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
cells_xtra_gw5a.v Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
CMakeLists.txt Use read_techlib where applicable 2026-06-25 08:49:02 +02:00
dsp_map.v gowin: format MULT instances 2026-02-12 13:35:49 +03:00
lutrams.txt gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
synth_gowin.cc Use read_techlib where applicable 2026-06-25 08:49:02 +02:00