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Code Activity
yosys/frontends
History
Miodrag Milanovic 219982941a Create a full copy of read_verilog to read_techlib
2026-06-25 08:48:07 +02:00
..
aiger read_aiger: import standard-cell mappings from ABC 2026-06-05 11:02:58 +01:00
aiger2 read_aiger: import standard-cell mappings from ABC 2026-06-05 11:02:58 +01:00
ast End of file fix 2026-06-23 07:23:41 +02:00
blif End of file fix 2026-06-23 07:23:41 +02:00
json Migrate build system to CMake 2026-06-03 08:58:10 +00:00
liberty End of file fix 2026-06-23 07:23:41 +02:00
rpc Migrate build system to CMake 2026-06-03 08:58:10 +00:00
rtlil Migrate build system to CMake 2026-06-03 08:58:10 +00:00
verific Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
verilog Create a full copy of read_verilog to read_techlib 2026-06-25 08:48:07 +02:00
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00