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yosys/passes
Marcin Kościelnicki f68985f997 deminout: prevent any constant assignment from demoting to input
Before this patch,

```
module top(inout io);
assign io = 1'bx;
endmodule
```

would have the `io` pin demoted to input (same happens for `1'bz`,
but not for `1'b0` or `1'b1`), resulting in check failures later on.

Part of fix for #1841.
2020-03-30 15:04:31 +02:00
..
cmds Explicit include of csignal 2020-03-28 09:49:08 +01:00
equiv xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
fsm fsm_extract: Initialize celltypes with full design. 2020-03-19 18:51:21 +01:00
hierarchy Merge pull request #1519 from YosysHQ/eddie/submod_po 2020-03-03 08:19:06 -08:00
memory Cleanup 2019-12-17 00:25:08 -08:00
opt ystests: fix write_smt2_write_smt2_cyclic_dependency_fail 2020-02-28 12:33:55 -08:00
pmgen Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly 2020-02-02 14:53:32 +00:00
proc proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage 2019-11-21 20:46:41 +00:00
sat Clean up pseudo-private member usage in passes/sat/miter.cc. 2020-03-19 07:07:22 +00:00
techmap deminout: prevent any constant assignment from demoting to input 2020-03-30 15:04:31 +02:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00