mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-29 15:37:59 +00:00
.. | ||
autowire.v | ||
README | ||
var_range.v |
This directory contains test cases that can't be tested using Icarus Verilog because they exceed the Verilog subset that is supported by Icarus Verilog.