Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. ... Fixes #2058.		2020-05-19 01:42:40 +02:00
..
tests
.gitignore
abc9_model.v	abc9_ops: add -prep_bypass for auto bypass boxes; refactor	2020-05-14 10:33:56 -07:00
arith_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
brams_init.py
cells_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
cells_sim.v	xilinx: gate specify/attributes from iverilog	2020-05-14 10:33:57 -07:00
cells_xtra.py
cells_xtra.v
lut4_lutrams.txt
lut6_lutrams.txt
lut_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
lutrams_map.v
Makefile.inc	abc9_ops: add -prep_bypass for auto bypass boxes; refactor	2020-05-14 10:33:56 -07:00
mux_map.v	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
synth_xilinx.cc	xilinx/ice40/ecp5: zinit requires selected wires, so select them all	2020-05-14 10:33:56 -07:00
xc2v_brams.txt
xc2v_brams_map.v
xc3s_mult_map.v
xc3sa_brams.txt
xc3sda_brams.txt
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v
xc6s_ff_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_ff_map.v
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v
xilinx_dffopt.cc	xilinx: improve xilinx_dffopt message	2020-04-22 16:25:23 -07:00