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yosys/frontends
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Zachary Snow f55fbb5803 verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 
- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.
2025-09-23 15:04:09 +02:00
..
aiger Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
aiger2 Remove .c_str() calls from log()/log_error() 2025-09-11 20:59:37 +00:00
ast verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections 2025-09-23 15:04:09 +02:00
blif Update frontends to avoid bits() 2025-09-16 03:17:23 +00:00
json Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
liberty Remove .c_str() calls from parameters to log_header() 2025-09-16 23:00:42 +00:00
rpc Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
rtlil Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
verific Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
verilog Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort 2025-09-22 11:14:39 +02:00