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yosys/techlibs/gowin/brams.txt
whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00

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Plaintext

bram $__GW1NR_SDP
init 1
abits 9 @a9d36
dbits 32 @a9d36
abits 10 @a10d18
dbits 16 @a10d18
abits 11 @a11d9
dbits 8 @a11d9
abits 12 @a12d4
dbits 4 @a12d4
abits 13 @a13d2
dbits 2 @a13d2
abits 14 @a14d1
dbits 1 @a14d1
groups 2
ports 1 1
wrmode 1 0
enable 4 1 @a9d36
enable 2 1 @a10d18
enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
match $__GW1NR_SDP
min bits 2048
min efficiency 5
shuffle_enable A
make_transp
endmatch