mirror of
https://github.com/YosysHQ/yosys
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550310e264
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
53 lines
715 B
Plaintext
53 lines
715 B
Plaintext
bram $__ECP5_PDPW16KD
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init 1
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abits 9
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dbits 36
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groups 2
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ports 1 1
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wrmode 1 0
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enable 4 1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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bram $__ECP5_DP16KD
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init 1
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abits 10 @a10d18
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dbits 18 @a10d18
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abits 11 @a11d9
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dbits 9 @a11d9
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abits 12 @a12d4
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dbits 4 @a12d4
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abits 13 @a13d2
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dbits 2 @a13d2
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abits 14 @a14d1
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dbits 1 @a14d1
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groups 2
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ports 1 1
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wrmode 1 0
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enable 2 1 @a10d18
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enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
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transp 0 2
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clocks 2 3
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clkpol 2 3
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endbram
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match $__ECP5_PDPW16KD
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min bits 2048
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min efficiency 5
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shuffle_enable A
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make_transp
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or_next_if_better
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endmatch
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match $__ECP5_DP16KD
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min bits 2048
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min efficiency 5
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shuffle_enable A
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endmatch
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