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yosys/techlibs/ecp5/abc9_unmap.v
2019-12-31 18:29:29 -08:00

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145 B
Verilog

// ---------------------------------------
module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
assign DO = $DO;
endmodule