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yosys/tests/arch
Eddie Hung f03e2c30aa
abc9: replace cell type/parameters if derived type already processed (#2991)
* Add close bracket

* Add testcase

* Replace cell type/param if in unmap_design

* Improve abc9_box error message too

* Update comment as per review
2021-09-09 10:05:55 -07:00
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anlogic memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
common Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
ecp5 abc9: replace cell type/parameters if derived type already processed (#2991) 2021-09-09 10:05:55 -07:00
efinix
gowin Gowin: deal with active-low tristate (#2971) 2021-08-20 21:21:06 +02:00
ice40 test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. 2021-08-11 14:52:38 +02:00
intel_alm memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
machxo2
nexus memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
quicklogic quicklogic: ABC9 synthesis 2021-04-17 20:54:58 +02:00
xilinx
run-test.sh Add default assignments to SB_LUT4 2021-04-20 12:46:21 +02:00