3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-03-25 05:48:38 +00:00
yosys/techlibs
Eddie Hung f03e2c30aa
abc9: replace cell type/parameters if derived type already processed (#2991)
* Add close bracket

* Add testcase

* Replace cell type/param if in unmap_design

* Improve abc9_box error message too

* Update comment as per review
2021-09-09 10:05:55 -07:00
..
achronix
anlogic
common Add v2 memory cells. 2021-08-11 13:34:10 +02:00
coolrunner2
easic
ecp5 abc9: replace cell type/parameters if derived type already processed (#2991) 2021-09-09 10:05:55 -07:00
efinix
gowin Gowin: deal with active-low tristate (#2971) 2021-08-20 21:21:06 +02:00
greenpak4
ice40 ice40: Fix typo in SB_CARRY specify for LP/UltraPlus 2021-08-17 14:33:30 +02:00
intel
intel_alm
machxo2
nexus Gowin: deal with active-low tristate (#2971) 2021-08-20 21:21:06 +02:00
quicklogic
sf2
xilinx
.gitignore