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f4298b057a
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
read_verilog ../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT3
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select -assert-count 3 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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# Can't run any sort of equivalence check because latches are blown to LUTs
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synth_quicklogic
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 2 t:LUT3
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select -assert-count 5 t:inpad
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select -assert-count 1 t:outpad
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select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
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