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https://github.com/YosysHQ/yosys
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Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
12 lines
561 B
Plaintext
12 lines
561 B
Plaintext
read_verilog ../common/add_sub.v
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hierarchy -top top
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equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 3 t:LUT2
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select -assert-count 4 t:LUT3
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select -assert-count 4 t:LUT4
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select -assert-count 8 t:inpad
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select -assert-count 8 t:outpad
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select -assert-none t:LUT2 t:LUT3 t:LUT4 t:inpad t:outpad %% t:* %D
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