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https://github.com/YosysHQ/yosys
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f4298b057a
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
37 lines
366 B
Verilog
37 lines
366 B
Verilog
module inv (
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output Q,
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input A
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);
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assign Q = A ? 0 : 1;
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endmodule
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module buff (
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output Q,
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input A
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);
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assign Q = A;
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endmodule
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module logic_0 (
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output A
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);
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assign A = 0;
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endmodule
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module logic_1 (
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output A
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);
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assign A = 1;
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endmodule
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module gclkbuff (
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input A,
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output Z
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);
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specify
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(A => Z) = 0;
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endspecify
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assign Z = A;
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endmodule
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