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tests
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DSP48E1 sim model: add SIMD tests
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2019-08-08 11:39:35 +01:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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abc_map.v
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Resolve TODO with pin assignments for SRL*
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2019-09-04 15:47:36 -07:00 |
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abc_model.v
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xilinx to use abc_map.v with -max_iter 1
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2019-08-20 19:47:11 -07:00 |
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abc_unmap.v
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xilinx to use abc_map.v with -max_iter 1
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2019-08-20 19:47:11 -07:00 |
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abc_xc7.box
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Add comments
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2019-09-02 12:22:15 -07:00 |
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abc_xc7.lut
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Simplify comment
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2019-06-17 19:14:41 -07:00 |
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abc_xc7_nowide.lut
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Add _nowide variants of LUT libraries in -nowidelut flows
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2019-06-26 10:23:29 -07:00 |
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arith_map.v
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Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21 16:19:45 -07:00 |
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brams_init.py
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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cells_map.v
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Use abc_{map,unmap,model}.v
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2019-08-20 12:39:11 -07:00 |
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cells_sim.v
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Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-05 13:01:27 -07:00 |
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cells_xtra.py
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move attributes to wires
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2019-08-13 19:36:59 +00:00 |
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cells_xtra.v
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Merge branch 'master' into xc7dsp
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2019-08-30 13:57:15 +01:00 |
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dsp_map.v
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Set USE_MULT and USE_SIMD
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2019-09-09 20:56:29 -07:00 |
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ff_map.v
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xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
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2019-07-11 21:13:12 +02:00 |
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lut_map.v
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Really permute Xilinx LUT mappings as default LUT6.I5:A6
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2019-06-18 11:48:48 -07:00 |
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lutrams.txt
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Work in progress for renaming labels/options in synth_xilinx
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2019-07-18 14:20:43 -07:00 |
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lutrams_map.v
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Work in progress for renaming labels/options in synth_xilinx
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2019-07-18 14:20:43 -07:00 |
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Makefile.inc
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Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-09-05 13:01:27 -07:00 |
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mux_map.v
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Change synth_xilinx's -nomux to -minmuxf <int>
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2019-06-24 10:04:01 -07:00 |
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synth_xilinx.cc
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Add comment for why opt_expr is necessary
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2019-09-10 14:11:56 -07:00 |
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xc6s_brams.txt
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc6s_brams_bb.v
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move attributes to wires
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2019-08-13 19:36:59 +00:00 |
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xc6s_brams_map.v
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RST -> RSTBRST for RAMB8BWER
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2019-07-29 16:05:44 -07:00 |
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xc7_brams.txt
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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xc7_brams_bb.v
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-28 15:19:10 -07:00 |
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xc7_brams_map.v
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
