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yosys/tests/techmap
2020-04-14 13:08:37 -07:00
..
.gitignore
abc9.ys Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
aigmap.ys
autopurge.ys
clkbufmap.ys clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
cmp2lcu.ys +/cmp2lcu.v to work efficiently for fully/partially constant inputs 2020-04-03 14:28:22 -07:00
dff2dffs.ys
dffinit.ys dffinit: Avoid setting init parameter to zero-length value. 2020-04-14 19:52:19 +02:00
extractinv.ys
iopadmap.ys iopadmap: Fix z assignment to inout port 2020-04-02 18:15:04 +02:00
mem_simple_4x1_cells.v
mem_simple_4x1_map.v
mem_simple_4x1_runtest.sh
mem_simple_4x1_tb.v
mem_simple_4x1_uut.v
recursive.v
recursive_map.v
recursive_runtest.sh
run-test.sh shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
shiftx2mux.ys shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
techmap_replace.ys techmap: Fix cell names with _TECHMAP_REPLACE_.* 2020-03-23 11:17:07 +01:00
wireinit.ys
zinit.ys tests: zinit for new types 2020-04-14 13:08:37 -07:00