mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-01 20:17:55 +00:00
If the `$ge` cell we are replacing has wide output port, the upper bits on the port should be driven to zero. That's not what a `$not` cell with a single-bit input does. Instead opt for a `$logic_not` cell, which does zero-pad its output. Fixes #3867. |
||
|---|---|---|
| .. | ||
| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| pmgen | ||
| proc | ||
| sat | ||
| techmap | ||
| tests | ||