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yosys/tests/various/signed.ys
Kamil Rakoczy 76a34dc5f3 Add signed/unsigned tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-26 15:38:20 +02:00

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# SV LRM A2.2.1
read_verilog -sv <<EOT
module test_signed();
parameter integer signed a = 0;
parameter integer unsigned b = 0;
endmodule
EOT
design -reset
read_verilog -sv <<EOT
module test_signed();
parameter logic signed [7:0] a = 0;
parameter logic unsigned [7:0] b = 0;
endmodule
EOT
design -reset
logger -expect error "syntax error, unexpected TOK_INTEGER" 1
read_verilog -sv <<EOT
module test_signed();
parameter signed integer a = 0;
parameter unsigned integer b = 0;
endmodule
EOT