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https://github.com/YosysHQ/yosys
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f2b88c23d4
Tested all the accepted configurations in eXpreso, disabling the RBRAM2 configs that fail to place, and increasing the cost for the double site TDP memories.
238 lines
5.6 KiB
Verilog
238 lines
5.6 KiB
Verilog
module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...);
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// libmap params
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parameter INIT = 0;
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parameter OPTION_MODE = "NONE";
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parameter OPTION_SIZE = "NONE";
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parameter OPTION_ERR = "NONE";
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH;
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parameter PORT_B_CLK_POL = 1;
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// needs -force-params
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parameter WIDTH = 40;
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parameter ABITS = 13;
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// non libmap params
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`ifdef IS_T40LP
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localparam NODE = "T40LP_Gen2.4";
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`endif
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`ifdef IS_T16FFC
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localparam NODE = "T16FFC_Gen2.4";
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`endif
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// localparam BRAM_MODE = "SDP_2048x36_BP";
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localparam BRAM_MODE = (OPTION_ERR!="NONE") ? {OPTION_MODE, "_", OPTION_SIZE, "_", OPTION_ERR} :
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{OPTION_MODE, "_", OPTION_SIZE};
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localparam PBITS = (OPTION_ERR=="BP") ? PORT_A_WR_EN_WIDTH : 1;
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// libmap ports
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input [ABITS-1:0] PORT_A_ADDR;
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input [WIDTH-1:0] PORT_A_WR_DATA;
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output [WIDTH-1:0] PORT_A_RD_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input [ABITS-1:0] PORT_B_ADDR;
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input [WIDTH-1:0] PORT_B_WR_DATA;
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output [WIDTH-1:0] PORT_B_RD_DATA;
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input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
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`ifdef IS_T40LP
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RBRAM
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`endif
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`ifdef IS_T16FFC
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RBRAM2
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`endif
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#(
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.TARGET_NODE(NODE),
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.BRAM_MODE(BRAM_MODE),
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.QA_REG((OPTION_ERR=="ECC") ? 1 : 0),
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.QB_REG((OPTION_ERR=="ECC") ? 1 : 0),
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.CLKA_INV(!PORT_A_CLK_POL),
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.CLKB_INV(!PORT_B_CLK_POL),
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.DATA_WIDTH(WIDTH),
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.ADDR_WIDTH(ABITS),
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.WE_WIDTH(PORT_A_WR_EN_WIDTH),
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.PERR_WIDTH(PBITS),
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)
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_TECHMAP_REPLACE_
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(
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.QA(PORT_A_RD_DATA),
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.DA(PORT_A_WR_DATA),
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.CEA(PORT_A_CLK_EN),
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.WEA(PORT_A_WR_EN),
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.AA(PORT_A_ADDR),
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.CLKA(PORT_A_CLK),
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.QB(PORT_B_RD_DATA),
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.DB(PORT_B_WR_DATA),
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.CEB(PORT_B_CLK_EN),
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.WEB(PORT_B_WR_EN),
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.AB(PORT_B_ADDR),
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.CLKB(PORT_B_CLK),
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);
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// check config
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generate
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if (PORT_A_WR_EN_WIDTH == PORT_B_WR_EN_WIDTH)
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case (BRAM_MODE)
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`ifdef IS_T40LP
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"SDP_1024x18_FP",
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"SDP_1024x16_BP",
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"SDP_2048x09",
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"SDP_4096x05",
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"SDP_1024x32_ECC",
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"SDP_1024x40",
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"SDP_1024x36_BP",
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"SDP_512x32_ECC",
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"SDP_512x36_BP",
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"SDP_2048x10",
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"SP_512x32_ECC",
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"SP_512x36_BP",
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"SP_1024x20",
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"SP2_512x18_BP",
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"SP2_1024x09",
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"SP2_2048x05": wire _TECHMAP_FAIL_ = 0;
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`endif
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`ifdef IS_T16FFC
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"TDP_2048x18_FP",
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"TDP_2048x16_BP",
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"TDP_4096x09",
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"TDP_8192x05",
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"TDP_2048x32_ECC",
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"TDP_2048x40",
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"TDP_2048x36_BP",
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"SDP_2048x18_FP",
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"SDP_2048x16_BP",
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// The following are rejected in eXpreso
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// "SDP_4096x09",
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// "SDP_8192x05",
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// "SDP_2048x32_ECC",
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// "SDP_2048x40",
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// "SDP_2048x36_BP",
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"SDP_1024x32_ECC",
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"SDP_1024x36_BP",
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"SDP_4096x10",
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"SP_1024x32_ECC",
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"SP_1024x36_BP",
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"SP_2048x20",
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"SP2_1024x18_BP",
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"SP2_2048x09",
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"SP2_4096x05": wire _TECHMAP_FAIL_ = 0;
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`endif
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default: wire _TECHMAP_FAIL_ = 1;
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endcase
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else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule
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module $__ANALOGDEVICES_BLOCKRAM_HALF_ (...);
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// libmap params
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parameter INIT = 0;
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parameter OPTION_MODE = "NONE";
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parameter OPTION_SIZE = "NONE";
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parameter OPTION_ERR = "NONE";
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH;
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parameter PORT_B_CLK_POL = 1;
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// needs -force-params
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parameter WIDTH = 40;
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parameter ABITS = 13;
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// libmap ports
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input [ABITS-1:0] PORT_A_ADDR;
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input [WIDTH-1:0] PORT_A_WR_DATA;
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output [WIDTH-1:0] PORT_A_RD_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input [ABITS-1:0] PORT_B_ADDR;
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input [WIDTH-1:0] PORT_B_WR_DATA;
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output [WIDTH-1:0] PORT_B_RD_DATA;
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input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
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$__ANALOGDEVICES_BLOCKRAM_FULL_
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# (
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.INIT(INIT),
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.OPTION_MODE(OPTION_MODE),
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.OPTION_SIZE(OPTION_SIZE),
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.OPTION_ERR(OPTION_ERR),
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.PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH),
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.PORT_A_CLK_POL(PORT_A_CLK_POL),
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.PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH),
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.PORT_B_CLK_POL(PORT_B_CLK_POL),
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.WIDTH(WIDTH),
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.ABITS(ABITS)
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)
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_TECHMAP_REPLACE_
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(
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.PORT_A_CLK(PORT_A_CLK),
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.PORT_A_CLK_EN(PORT_A_CLK_EN),
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.PORT_A_ADDR(PORT_A_ADDR),
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.PORT_A_WR_DATA(PORT_A_WR_DATA),
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.PORT_A_RD_DATA(PORT_A_RD_DATA),
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.PORT_A_WR_EN(PORT_A_WR_EN),
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.PORT_B_CLK(PORT_B_CLK),
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.PORT_B_CLK_EN(PORT_B_CLK_EN),
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.PORT_B_ADDR(PORT_B_ADDR),
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.PORT_B_WR_DATA(PORT_B_WR_DATA),
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.PORT_B_RD_DATA(PORT_B_RD_DATA),
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.PORT_B_WR_EN(PORT_B_WR_EN)
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);
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endmodule
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module $__ANALOGDEVICES_BLOCKRAM_QUARTER_ (...);
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// libmap params
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parameter INIT = 0;
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parameter OPTION_MODE = "NONE";
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parameter OPTION_SIZE = "NONE";
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parameter OPTION_ERR = "NONE";
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_CLK_POL = 1;
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parameter PORT_B_WR_EN_WIDTH = PORT_A_WR_EN_WIDTH;
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parameter PORT_B_CLK_POL = 1;
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// needs -force-params
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parameter WIDTH = 40;
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parameter ABITS = 13;
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// libmap ports
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input [ABITS-1:0] PORT_A_ADDR;
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input [WIDTH-1:0] PORT_A_WR_DATA;
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output [WIDTH-1:0] PORT_A_RD_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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$__ANALOGDEVICES_BLOCKRAM_FULL_
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# (
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.INIT(INIT),
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.OPTION_MODE(OPTION_MODE),
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.OPTION_SIZE(OPTION_SIZE),
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.OPTION_ERR(OPTION_ERR),
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.PORT_A_WR_EN_WIDTH(PORT_A_WR_EN_WIDTH),
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.PORT_A_CLK_POL(PORT_A_CLK_POL),
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.PORT_B_WR_EN_WIDTH(PORT_B_WR_EN_WIDTH),
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.PORT_B_CLK_POL(PORT_B_CLK_POL),
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.WIDTH(WIDTH),
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.ABITS(ABITS)
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)
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_TECHMAP_REPLACE_
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(
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.PORT_A_CLK(PORT_A_CLK),
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.PORT_A_CLK_EN(PORT_A_CLK_EN),
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.PORT_A_ADDR(PORT_A_ADDR),
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.PORT_A_WR_DATA(PORT_A_WR_DATA),
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.PORT_A_RD_DATA(PORT_A_RD_DATA),
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.PORT_A_WR_EN(PORT_A_WR_EN),
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);
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endmodule
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