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Most of the word/coarse level cells have an assigned group and individual page. The gate/fine level cells are all on one page. Fix links to `cell_library.rst`.
281 lines
10 KiB
ReStructuredText
281 lines
10 KiB
ReStructuredText
.. role:: verilog(code)
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:language: Verilog
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.. _sec:memcells:
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Memories
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~~~~~~~~
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Memories are either represented using ``RTLIL::Memory`` objects, `$memrd_v2`,
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`$memwr_v2`, and `$meminit_v2` cells, or by `$mem_v2` cells alone.
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In the first alternative the ``RTLIL::Memory`` objects hold the general metadata
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for the memory (bit width, size in number of words, etc.) and for each port a
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`$memrd_v2` (read port) or `$memwr_v2` (write port) cell is created. Having
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individual cells for read and write ports has the advantage that they can be
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consolidated using resource sharing passes. In some cases this drastically
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reduces the number of required ports on the memory cell. In this alternative,
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memory initialization data is represented by `$meminit_v2` cells, which allow
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delaying constant folding for initialization addresses and data until after the
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frontend finishes.
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The `$memrd_v2` cells have a clock input ``CLK``, an enable input ``EN``, an
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address input ``ADDR``, a data output ``DATA``, an asynchronous reset input
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``ARST``, and a synchronous reset input ``SRST``. They also have the following
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parameters:
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``MEMID``
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The name of the ``RTLIL::Memory`` object that is associated with this read
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port.
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``ABITS``
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The number of address bits (width of the ``ADDR`` input port).
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``WIDTH``
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The number of data bits (width of the ``DATA`` output port). Note that this
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may be a power-of-two multiple of the underlying memory's width -- such ports
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are called wide ports and access an aligned group of cells at once. In this
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case, the corresponding low bits of ``ADDR`` must be tied to 0.
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``CLK_ENABLE``
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When this parameter is non-zero, the clock is used. Otherwise this read port
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is asynchronous and the ``CLK`` input is not used.
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``CLK_POLARITY``
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Clock is active on the positive edge if this parameter has the value ``1'b1``
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and on the negative edge if this parameter is ``1'b0``.
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``TRANSPARENCY_MASK``
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This parameter is a bitmask of write ports that this read port is transparent
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with. The bits of this parameter are indexed by the write port's ``PORTID``
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parameter. Transparency can only be enabled between synchronous ports sharing
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a clock domain. When transparency is enabled for a given port pair, a read
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and write to the same address in the same cycle will return the new value.
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Otherwise the old value is returned.
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``COLLISION_X_MASK``
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This parameter is a bitmask of write ports that have undefined collision
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behavior with this port. The bits of this parameter are indexed by the write
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port's ``PORTID`` parameter. This behavior can only be enabled between
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synchronous ports sharing a clock domain. When undefined collision is enabled
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for a given port pair, a read and write to the same address in the same cycle
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will return the undefined (all-X) value.This option is exclusive (for a given
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port pair) with the transparency option.
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``ARST_VALUE``
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Whenever the ``ARST`` input is asserted, the data output will be reset to
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this value. Only used for synchronous ports.
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``SRST_VALUE``
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Whenever the ``SRST`` input is synchronously asserted, the data output will
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be reset to this value. Only used for synchronous ports.
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``INIT_VALUE``
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The initial value of the data output, for synchronous ports.
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``CE_OVER_SRST``
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If this parameter is non-zero, the ``SRST`` input is only recognized when
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``EN`` is true. Otherwise, ``SRST`` is recognized regardless of ``EN``.
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The `$memwr_v2` cells have a clock input ``CLK``, an enable input ``EN`` (one
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enable bit for each data bit), an address input ``ADDR`` and a data input
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``DATA``. They also have the following parameters:
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``MEMID``
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The name of the ``RTLIL::Memory`` object that is associated with this write
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port.
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``ABITS``
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The number of address bits (width of the ``ADDR`` input port).
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``WIDTH``
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The number of data bits (width of the ``DATA`` output port). Like with
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`$memrd_v2` cells, the width is allowed to be any power-of-two multiple of
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memory width, with the corresponding restriction on address.
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``CLK_ENABLE``
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When this parameter is non-zero, the clock is used. Otherwise this write port
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is asynchronous and the ``CLK`` input is not used.
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``CLK_POLARITY``
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Clock is active on positive edge if this parameter has the value ``1'b1`` and
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on the negative edge if this parameter is ``1'b0``.
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``PORTID``
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An identifier for this write port, used to index write port bit mask
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parameters.
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``PRIORITY_MASK``
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This parameter is a bitmask of write ports that this write port has priority
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over in case of writing to the same address. The bits of this parameter are
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indexed by the other write port's ``PORTID`` parameter. Write ports can only
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have priority over write ports with lower port ID. When two ports write to
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the same address and neither has priority over the other, the result is
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undefined. Priority can only be set between two synchronous ports sharing
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the same clock domain.
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The `$meminit_v2` cells have an address input ``ADDR``, a data input ``DATA``,
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with the width of the ``DATA`` port equal to ``WIDTH`` parameter times ``WORDS``
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parameter, and a bit enable mask input ``EN`` with width equal to ``WIDTH``
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parameter. All three of the inputs must resolve to a constant for synthesis to
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succeed.
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``MEMID``
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The name of the ``RTLIL::Memory`` object that is associated with this
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initialization cell.
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``ABITS``
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The number of address bits (width of the ``ADDR`` input port).
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``WIDTH``
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The number of data bits per memory location.
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``WORDS``
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The number of consecutive memory locations initialized by this cell.
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``PRIORITY``
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The cell with the higher integer value in this parameter wins an
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initialization conflict.
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The HDL frontend models a memory using ``RTLIL::Memory`` objects and
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asynchronous `$memrd_v2` and `$memwr_v2` cells. The `memory` pass (i.e. its
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various sub-passes) migrates `$dff` cells into the `$memrd_v2` and `$memwr_v2`
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cells making them synchronous, then converts them to a single `$mem_v2` cell and
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(optionally) maps this cell type to `$dff` cells for the individual words and
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multiplexer-based address decoders for the read and write interfaces. When the
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last step is disabled or not possible, a `$mem_v2` cell is left in the design.
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The `$mem_v2` cell provides the following parameters:
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``MEMID``
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The name of the original ``RTLIL::Memory`` object that became this `$mem_v2`
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cell.
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``SIZE``
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The number of words in the memory.
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``ABITS``
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The number of address bits.
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``WIDTH``
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The number of data bits per word.
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``INIT``
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The initial memory contents.
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``RD_PORTS``
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The number of read ports on this memory cell.
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``RD_WIDE_CONTINUATION``
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This parameter is ``RD_PORTS`` bits wide, containing a bitmask of "wide
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continuation" read ports. Such ports are used to represent the extra data
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bits of wide ports in the combined cell, and must have all control signals
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identical with the preceding port, except for address, which must have the
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proper sub-cell address encoded in the low bits.
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``RD_CLK_ENABLE``
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This parameter is ``RD_PORTS`` bits wide, containing a clock enable bit for
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each read port.
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``RD_CLK_POLARITY``
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This parameter is ``RD_PORTS`` bits wide, containing a clock polarity bit for
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each read port.
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``RD_TRANSPARENCY_MASK``
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This parameter is ``RD_PORTS*WR_PORTS`` bits wide, containing a concatenation
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of all ``TRANSPARENCY_MASK`` values of the original `$memrd_v2` cells.
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``RD_COLLISION_X_MASK``
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This parameter is ``RD_PORTS*WR_PORTS`` bits wide, containing a concatenation
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of all ``COLLISION_X_MASK`` values of the original `$memrd_v2` cells.
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``RD_CE_OVER_SRST``
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This parameter is ``RD_PORTS`` bits wide, determining relative synchronous
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reset and enable priority for each read port.
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``RD_INIT_VALUE``
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This parameter is ``RD_PORTS*WIDTH`` bits wide, containing the initial value
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for each synchronous read port.
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``RD_ARST_VALUE``
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This parameter is ``RD_PORTS*WIDTH`` bits wide, containing the asynchronous
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reset value for each synchronous read port.
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``RD_SRST_VALUE``
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This parameter is ``RD_PORTS*WIDTH`` bits wide, containing the synchronous
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reset value for each synchronous read port.
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``WR_PORTS``
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The number of write ports on this memory cell.
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``WR_WIDE_CONTINUATION``
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This parameter is ``WR_PORTS`` bits wide, containing a bitmask of "wide
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continuation" write ports.
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``WR_CLK_ENABLE``
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This parameter is ``WR_PORTS`` bits wide, containing a clock enable bit for
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each write port.
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``WR_CLK_POLARITY``
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This parameter is ``WR_PORTS`` bits wide, containing a clock polarity bit for
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each write port.
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``WR_PRIORITY_MASK``
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This parameter is ``WR_PORTS*WR_PORTS`` bits wide, containing a concatenation
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of all ``PRIORITY_MASK`` values of the original `$memwr_v2` cells.
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The `$mem_v2` cell has the following ports:
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``RD_CLK``
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This input is ``RD_PORTS`` bits wide, containing all clock signals for the
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read ports.
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``RD_EN``
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This input is ``RD_PORTS`` bits wide, containing all enable signals for the
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read ports.
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``RD_ADDR``
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This input is ``RD_PORTS*ABITS`` bits wide, containing all address signals
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for the read ports.
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``RD_DATA``
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This output is ``RD_PORTS*WIDTH`` bits wide, containing all data signals for
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the read ports.
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``RD_ARST``
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This input is ``RD_PORTS`` bits wide, containing all asynchronous reset
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signals for the read ports.
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``RD_SRST``
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This input is ``RD_PORTS`` bits wide, containing all synchronous reset
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signals for the read ports.
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``WR_CLK``
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This input is ``WR_PORTS`` bits wide, containing all clock signals for the
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write ports.
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``WR_EN``
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This input is ``WR_PORTS*WIDTH`` bits wide, containing all enable signals for
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the write ports.
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``WR_ADDR``
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This input is ``WR_PORTS*ABITS`` bits wide, containing all address signals
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for the write ports.
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``WR_DATA``
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This input is ``WR_PORTS*WIDTH`` bits wide, containing all data signals for
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the write ports.
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The `memory_collect` pass can be used to convert discrete `$memrd_v2`,
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`$memwr_v2`, and `$meminit_v2` cells belonging to the same memory to a single
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`$mem_v2` cell, whereas the `memory_unpack` pass performs the inverse operation.
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The `memory_dff` pass can combine asynchronous memory ports that are fed by or
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feeding registers into synchronous memory ports. The `memory_bram` pass can be
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used to recognize `$mem_v2` cells that can be implemented with a block RAM
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resource on an FPGA. The `memory_map` pass can be used to implement `$mem_v2`
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cells as basic logic: word-wide DFFs and address decoders.
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.. autocellgroup:: mem
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:members:
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:source:
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:linenos:
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