mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
15 lines
217 B
Verilog
15 lines
217 B
Verilog
module reg_seq_example( clk, reset, d, q);
|
|
input clk, reset, d;
|
|
output q;
|
|
|
|
reg q;
|
|
wire clk, reset, d;
|
|
|
|
always @ (posedge clk or posedge reset)
|
|
if (reset) begin
|
|
q <= 1'b0;
|
|
end else begin
|
|
q <= d;
|
|
end
|
|
|
|
endmodule
|