3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-10 02:51:00 +00:00
yosys/manual
Eddie Hung 6d4b6b1e69
Merge pull request #1575 from rodrigomelo9/master
Fixed some missing "verilog_" in documentation
2019-12-15 19:00:34 -08:00
..
APPNOTE_011_Design_Investigation
CHAPTER_Eval
CHAPTER_Prog
CHAPTER_StateOfTheArt
PRESENTATION_ExAdv
PRESENTATION_ExOth Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
PRESENTATION_ExSyn
PRESENTATION_Intro
PRESENTATION_Prog
.gitignore
APPNOTE_010_Verilog_to_BLIF.tex
APPNOTE_011_Design_Investigation.tex
APPNOTE_012_Verilog_to_BTOR.tex
appnotes.sh
CHAPTER_Appnotes.tex
CHAPTER_Approach.tex
CHAPTER_Auxlibs.tex
CHAPTER_Auxprogs.tex
CHAPTER_Basics.tex
CHAPTER_CellLib.tex
CHAPTER_Eval.tex
CHAPTER_Intro.tex
CHAPTER_Optimize.tex
CHAPTER_Overview.tex
CHAPTER_Prog.tex
CHAPTER_StateOfTheArt.tex
CHAPTER_Techmap.tex
CHAPTER_Verilog.tex
clean.sh
command-reference-manual.tex
literature.bib
manual.sh
manual.tex
presentation.sh
presentation.tex
PRESENTATION_ExAdv.tex
PRESENTATION_ExOth.tex
PRESENTATION_ExSyn.tex
PRESENTATION_Intro.tex
PRESENTATION_Prog.tex
weblinks.bib