mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
3aa4484a3c
o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
618 lines
20 KiB
C++
618 lines
20 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "simplemap.h"
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#include "kernel/sigtools.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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USING_YOSYS_NAMESPACE
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YOSYS_NAMESPACE_BEGIN
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void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a[i]);
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gate->setPort("\\Y", sig_y[i]);
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}
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}
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void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
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module->connect(RTLIL::SigSig(sig_y, sig_a));
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}
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void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
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sig_b.extend_u0(GetSize(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
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if (cell->type == "$xnor")
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_t[i]);
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gate->setPort("\\Y", sig_y[i]);
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}
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sig_y = sig_t;
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}
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std::string gate_type;
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if (cell->type == "$and") gate_type = "$_AND_";
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if (cell->type == "$or") gate_type = "$_OR_";
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if (cell->type == "$xor") gate_type = "$_XOR_";
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if (cell->type == "$xnor") gate_type = "$_XOR_";
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log_assert(!gate_type.empty());
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a[i]);
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gate->setPort("\\B", sig_b[i]);
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gate->setPort("\\Y", sig_y[i]);
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}
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}
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void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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if (sig_y.size() == 0)
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return;
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if (sig_a.size() == 0) {
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if (cell->type == "$reduce_and") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == "$reduce_or") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == "$reduce_xor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == "$reduce_xnor") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == "$reduce_bool") module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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return;
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}
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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std::string gate_type;
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if (cell->type == "$reduce_and") gate_type = "$_AND_";
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if (cell->type == "$reduce_or") gate_type = "$_OR_";
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if (cell->type == "$reduce_xor") gate_type = "$_XOR_";
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if (cell->type == "$reduce_xnor") gate_type = "$_XOR_";
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if (cell->type == "$reduce_bool") gate_type = "$_OR_";
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log_assert(!gate_type.empty());
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RTLIL::Cell *last_output_cell = NULL;
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while (sig_a.size() > 1)
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
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for (int i = 0; i < sig_a.size(); i += 2)
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{
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if (i+1 == sig_a.size()) {
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sig_t.append(sig_a[i]);
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continue;
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a[i]);
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gate->setPort("\\B", sig_a[i+1]);
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gate->setPort("\\Y", sig_t[i/2]);
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last_output_cell = gate;
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}
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sig_a = sig_t;
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}
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if (cell->type == "$reduce_xnor") {
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a);
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gate->setPort("\\Y", sig_t);
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last_output_cell = gate;
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sig_a = sig_t;
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}
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if (last_output_cell == NULL) {
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module->connect(RTLIL::SigSig(sig_y, sig_a));
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} else {
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last_output_cell->setPort("\\Y", sig_y);
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}
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}
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static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell *cell)
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{
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while (sig.size() > 1)
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
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for (int i = 0; i < sig.size(); i += 2)
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{
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if (i+1 == sig.size()) {
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sig_t.append(sig[i]);
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continue;
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_OR_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig[i]);
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gate->setPort("\\B", sig[i+1]);
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gate->setPort("\\Y", sig_t[i/2]);
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}
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sig = sig_t;
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}
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if (sig.size() == 0)
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sig = RTLIL::SigSpec(0, 1);
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}
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void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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logic_reduce(module, sig_a, cell);
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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if (sig_y.size() == 0)
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return;
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a);
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gate->setPort("\\Y", sig_y);
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}
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void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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logic_reduce(module, sig_a, cell);
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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logic_reduce(module, sig_b, cell);
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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if (sig_y.size() == 0)
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return;
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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std::string gate_type;
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if (cell->type == "$logic_and") gate_type = "$_AND_";
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if (cell->type == "$logic_or") gate_type = "$_OR_";
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log_assert(!gate_type.empty());
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a);
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gate->setPort("\\B", sig_b);
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gate->setPort("\\Y", sig_y);
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}
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void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
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bool is_ne = cell->type == "$ne" || cell->type == "$nex";
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RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
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RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
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xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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simplemap_bitop(module, xor_cell);
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module->remove(xor_cell);
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RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
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RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
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reduce_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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simplemap_reduce(module, reduce_cell);
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module->remove(reduce_cell);
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if (!is_ne) {
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RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
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not_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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simplemap_lognot(module, not_cell);
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module->remove(not_cell);
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}
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}
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void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a[i]);
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gate->setPort("\\B", sig_b[i]);
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gate->setPort("\\S", cell->getPort("\\S"));
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gate->setPort("\\Y", sig_y[i]);
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}
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}
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void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_e = cell->getPort("\\EN");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_TBUF_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", sig_a[i]);
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gate->setPort("\\E", sig_e);
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gate->setPort("\\Y", sig_y[i]);
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}
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}
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void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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SigSpec lut_ctrl = cell->getPort("\\A");
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SigSpec lut_data = cell->getParam("\\LUT");
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lut_data.extend_u0(1 << cell->getParam("\\WIDTH").as_int());
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for (int idx = 0; GetSize(lut_data) > 1; idx++) {
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SigSpec sig_s = lut_ctrl[idx];
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SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
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for (int i = 0; i < GetSize(lut_data); i += 2) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\A", lut_data[i]);
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gate->setPort("\\B", lut_data[i+1]);
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gate->setPort("\\S", lut_ctrl[idx]);
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gate->setPort("\\Y", new_lut_data[i/2]);
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}
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lut_data = new_lut_data;
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}
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module->connect(cell->getPort("\\Y"), lut_data);
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}
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void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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SigSpec ctrl = cell->getPort("\\A");
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SigSpec table = cell->getParam("\\TABLE");
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int width = cell->getParam("\\WIDTH").as_int();
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int depth = cell->getParam("\\DEPTH").as_int();
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table.extend_u0(2 * width * depth);
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SigSpec products;
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for (int i = 0; i < depth; i++) {
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SigSpec in, pat;
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for (int j = 0; j < width; j++) {
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if (table[2*i*width + 2*j + 0] == State::S1) {
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in.append(ctrl[j]);
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pat.append(State::S0);
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}
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if (table[2*i*width + 2*j + 1] == State::S1) {
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in.append(ctrl[j]);
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pat.append(State::S1);
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}
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}
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products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
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}
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module->connect(cell->getPort("\\Y"), module->ReduceOr(NEW_ID, products));
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}
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void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int offset = cell->parameters.at("\\OFFSET").as_int();
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
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}
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void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_ab = cell->getPort("\\A");
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sig_ab.append(cell->getPort("\\B"));
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RTLIL::SigSpec sig_y = cell->getPort("\\Y");
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module->connect(RTLIL::SigSig(sig_y, sig_ab));
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}
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void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
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char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_s = cell->getPort("\\SET");
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RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
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RTLIL::SigSpec sig_q = cell->getPort("\\Q");
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std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\S", sig_s[i]);
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gate->setPort("\\R", sig_r[i]);
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gate->setPort("\\Q", sig_q[i]);
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}
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}
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void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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RTLIL::SigSpec sig_d = cell->getPort("\\D");
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RTLIL::SigSpec sig_q = cell->getPort("\\Q");
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std::string gate_type = "$_FF_";
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for (int i = 0; i < width; i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
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gate->setPort("\\D", sig_d[i]);
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gate->setPort("\\Q", sig_q[i]);
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}
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}
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void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
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RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
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RTLIL::SigSpec sig_d = cell->getPort("\\D");
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RTLIL::SigSpec sig_q = cell->getPort("\\Q");
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|
std::string gate_type = stringf("$_DFF_%c_", clk_pol);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
|
|
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
|
|
gate->setPort("\\C", sig_clk);
|
|
gate->setPort("\\D", sig_d[i]);
|
|
gate->setPort("\\Q", sig_q[i]);
|
|
}
|
|
}
|
|
|
|
void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
|
|
{
|
|
int width = cell->parameters.at("\\WIDTH").as_int();
|
|
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
|
|
char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
|
|
|
|
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
|
|
RTLIL::SigSpec sig_en = cell->getPort("\\EN");
|
|
RTLIL::SigSpec sig_d = cell->getPort("\\D");
|
|
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
|
|
|
|
std::string gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
|
|
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
|
|
gate->setPort("\\C", sig_clk);
|
|
gate->setPort("\\E", sig_en);
|
|
gate->setPort("\\D", sig_d[i]);
|
|
gate->setPort("\\Q", sig_q[i]);
|
|
}
|
|
}
|
|
|
|
void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
|
|
{
|
|
int width = cell->parameters.at("\\WIDTH").as_int();
|
|
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
|
|
char set_pol = cell->parameters.at("\\SET_POLARITY").as_bool() ? 'P' : 'N';
|
|
char clr_pol = cell->parameters.at("\\CLR_POLARITY").as_bool() ? 'P' : 'N';
|
|
|
|
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
|
|
RTLIL::SigSpec sig_s = cell->getPort("\\SET");
|
|
RTLIL::SigSpec sig_r = cell->getPort("\\CLR");
|
|
RTLIL::SigSpec sig_d = cell->getPort("\\D");
|
|
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
|
|
|
|
std::string gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
|
|
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
|
|
gate->setPort("\\C", sig_clk);
|
|
gate->setPort("\\S", sig_s[i]);
|
|
gate->setPort("\\R", sig_r[i]);
|
|
gate->setPort("\\D", sig_d[i]);
|
|
gate->setPort("\\Q", sig_q[i]);
|
|
}
|
|
}
|
|
|
|
void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
|
|
{
|
|
int width = cell->parameters.at("\\WIDTH").as_int();
|
|
char clk_pol = cell->parameters.at("\\CLK_POLARITY").as_bool() ? 'P' : 'N';
|
|
char rst_pol = cell->parameters.at("\\ARST_POLARITY").as_bool() ? 'P' : 'N';
|
|
|
|
std::vector<RTLIL::State> rst_val = cell->parameters.at("\\ARST_VALUE").bits;
|
|
while (int(rst_val.size()) < width)
|
|
rst_val.push_back(RTLIL::State::S0);
|
|
|
|
RTLIL::SigSpec sig_clk = cell->getPort("\\CLK");
|
|
RTLIL::SigSpec sig_rst = cell->getPort("\\ARST");
|
|
RTLIL::SigSpec sig_d = cell->getPort("\\D");
|
|
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
|
|
|
|
std::string gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
|
|
std::string gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
|
|
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
|
|
gate->setPort("\\C", sig_clk);
|
|
gate->setPort("\\R", sig_rst);
|
|
gate->setPort("\\D", sig_d[i]);
|
|
gate->setPort("\\Q", sig_q[i]);
|
|
}
|
|
}
|
|
|
|
void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
|
|
{
|
|
int width = cell->parameters.at("\\WIDTH").as_int();
|
|
char en_pol = cell->parameters.at("\\EN_POLARITY").as_bool() ? 'P' : 'N';
|
|
|
|
RTLIL::SigSpec sig_en = cell->getPort("\\EN");
|
|
RTLIL::SigSpec sig_d = cell->getPort("\\D");
|
|
RTLIL::SigSpec sig_q = cell->getPort("\\Q");
|
|
|
|
std::string gate_type = stringf("$_DLATCH_%c_", en_pol);
|
|
|
|
for (int i = 0; i < width; i++) {
|
|
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
|
|
gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
|
|
gate->setPort("\\E", sig_en);
|
|
gate->setPort("\\D", sig_d[i]);
|
|
gate->setPort("\\Q", sig_q[i]);
|
|
}
|
|
}
|
|
|
|
void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
|
|
{
|
|
mappers["$not"] = simplemap_not;
|
|
mappers["$pos"] = simplemap_pos;
|
|
mappers["$and"] = simplemap_bitop;
|
|
mappers["$or"] = simplemap_bitop;
|
|
mappers["$xor"] = simplemap_bitop;
|
|
mappers["$xnor"] = simplemap_bitop;
|
|
mappers["$reduce_and"] = simplemap_reduce;
|
|
mappers["$reduce_or"] = simplemap_reduce;
|
|
mappers["$reduce_xor"] = simplemap_reduce;
|
|
mappers["$reduce_xnor"] = simplemap_reduce;
|
|
mappers["$reduce_bool"] = simplemap_reduce;
|
|
mappers["$logic_not"] = simplemap_lognot;
|
|
mappers["$logic_and"] = simplemap_logbin;
|
|
mappers["$logic_or"] = simplemap_logbin;
|
|
mappers["$eq"] = simplemap_eqne;
|
|
mappers["$eqx"] = simplemap_eqne;
|
|
mappers["$ne"] = simplemap_eqne;
|
|
mappers["$nex"] = simplemap_eqne;
|
|
mappers["$mux"] = simplemap_mux;
|
|
mappers["$tribuf"] = simplemap_tribuf;
|
|
mappers["$lut"] = simplemap_lut;
|
|
mappers["$sop"] = simplemap_sop;
|
|
mappers["$slice"] = simplemap_slice;
|
|
mappers["$concat"] = simplemap_concat;
|
|
mappers["$sr"] = simplemap_sr;
|
|
mappers["$ff"] = simplemap_ff;
|
|
mappers["$dff"] = simplemap_dff;
|
|
mappers["$dffe"] = simplemap_dffe;
|
|
mappers["$dffsr"] = simplemap_dffsr;
|
|
mappers["$adff"] = simplemap_adff;
|
|
mappers["$dlatch"] = simplemap_dlatch;
|
|
}
|
|
|
|
void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
|
|
{
|
|
static std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
|
|
static bool initialized_mappers = false;
|
|
|
|
if (!initialized_mappers) {
|
|
simplemap_get_mappers(mappers);
|
|
initialized_mappers = true;
|
|
}
|
|
|
|
mappers.at(cell->type)(module, cell);
|
|
}
|
|
|
|
YOSYS_NAMESPACE_END
|
|
PRIVATE_NAMESPACE_BEGIN
|
|
|
|
struct SimplemapPass : public Pass {
|
|
SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" simplemap [selection]\n");
|
|
log("\n");
|
|
log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
|
|
log("primitives. The following internal cell types are mapped by this pass:\n");
|
|
log("\n");
|
|
log(" $not, $pos, $and, $or, $xor, $xnor\n");
|
|
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
|
|
log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
|
|
log(" $sr, $ff, $dff, $dffsr, $adff, $dlatch\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
|
|
extra_args(args, 1, design);
|
|
|
|
std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
|
|
simplemap_get_mappers(mappers);
|
|
|
|
for (auto mod : design->modules()) {
|
|
if (!design->selected(mod))
|
|
continue;
|
|
std::vector<RTLIL::Cell*> cells = mod->cells();
|
|
for (auto cell : cells) {
|
|
if (mappers.count(cell->type) == 0)
|
|
continue;
|
|
if (!design->selected(mod, cell))
|
|
continue;
|
|
log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
|
|
mappers.at(cell->type)(mod, cell);
|
|
mod->remove(cell);
|
|
}
|
|
}
|
|
}
|
|
} SimplemapPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|