mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
3aa4484a3c
o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
419 lines
15 KiB
C++
419 lines
15 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void split_portname_pair(std::string &port1, std::string &port2)
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{
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size_t pos = port1.find_first_of(':');
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if (pos != std::string::npos) {
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port2 = port1.substr(pos+1);
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port1 = port1.substr(0, pos);
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}
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}
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struct IopadmapPass : public Pass {
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IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
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void help() YS_OVERRIDE
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{
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log("\n");
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log(" iopadmap [options] [selection]\n");
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log("\n");
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log("Map module inputs/outputs to PAD cells from a library. This pass\n");
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log("can only map to very simple PAD cells. Use 'techmap' to further map\n");
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log("the resulting cells to more sophisticated PAD cells.\n");
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log("\n");
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log(" -inpad <celltype> <portname>[:<portname>]\n");
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log(" Map module input ports to the given cell type with the\n");
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log(" given output port name. if a 2nd portname is given, the\n");
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log(" signal is passed through the pad call, using the 2nd\n");
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log(" portname as the port facing the module port.\n");
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log("\n");
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log(" -outpad <celltype> <portname>[:<portname>]\n");
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log(" -inoutpad <celltype> <portname>[:<portname>]\n");
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log(" Similar to -inpad, but for output and inout ports.\n");
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log("\n");
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log(" -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
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log(" Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
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log(" over the other -outpad cell. The first portname is the enable input\n");
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log(" of the tristate driver.\n");
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log("\n");
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log(" -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
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log(" Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
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log(" over the other -inoutpad cell. The first portname is the enable input\n");
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log(" of the tristate driver and the 2nd portname is the internal output\n");
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log(" buffering the external signal.\n");
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log("\n");
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log(" -widthparam <param_name>\n");
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log(" Use the specified parameter name to set the port width.\n");
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log("\n");
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log(" -nameparam <param_name>\n");
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log(" Use the specified parameter to set the port name.\n");
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log("\n");
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log(" -bits\n");
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log(" create individual bit-wide buffers even for ports that\n");
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log(" are wider. (the default behavior is to create word-wide\n");
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log(" buffers using -widthparam to set the word size on the cell.)\n");
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log("\n");
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log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
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std::string inpad_celltype, inpad_portname, inpad_portname2;
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std::string outpad_celltype, outpad_portname, outpad_portname2;
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std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
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std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
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std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
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std::string widthparam, nameparam;
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bool flag_bits = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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if (arg == "-inpad" && argidx+2 < args.size()) {
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inpad_celltype = args[++argidx];
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inpad_portname = args[++argidx];
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split_portname_pair(inpad_portname, inpad_portname2);
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continue;
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}
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if (arg == "-outpad" && argidx+2 < args.size()) {
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outpad_celltype = args[++argidx];
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outpad_portname = args[++argidx];
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split_portname_pair(outpad_portname, outpad_portname2);
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continue;
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}
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if (arg == "-inoutpad" && argidx+2 < args.size()) {
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inoutpad_celltype = args[++argidx];
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inoutpad_portname = args[++argidx];
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split_portname_pair(inoutpad_portname, inoutpad_portname2);
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continue;
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}
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if (arg == "-toutpad" && argidx+2 < args.size()) {
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toutpad_celltype = args[++argidx];
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toutpad_portname = args[++argidx];
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split_portname_pair(toutpad_portname, toutpad_portname2);
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split_portname_pair(toutpad_portname2, toutpad_portname3);
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continue;
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}
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if (arg == "-tinoutpad" && argidx+2 < args.size()) {
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tinoutpad_celltype = args[++argidx];
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tinoutpad_portname = args[++argidx];
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split_portname_pair(tinoutpad_portname, tinoutpad_portname2);
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split_portname_pair(tinoutpad_portname2, tinoutpad_portname3);
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split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
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continue;
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}
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if (arg == "-widthparam" && argidx+1 < args.size()) {
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widthparam = args[++argidx];
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continue;
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}
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if (arg == "-nameparam" && argidx+1 < args.size()) {
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nameparam = args[++argidx];
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continue;
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}
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if (arg == "-bits") {
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flag_bits = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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dict<IdString, pool<int>> skip_wires;
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pool<SigBit> skip_wire_bits;
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SigMap sigmap(module);
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for (auto cell : module->cells())
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{
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if (cell->type == RTLIL::escape_id(inpad_celltype) && cell->hasPort(RTLIL::escape_id(inpad_portname2)))
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for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inpad_portname2))))
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skip_wire_bits.insert(bit);
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if (cell->type == RTLIL::escape_id(outpad_celltype) && cell->hasPort(RTLIL::escape_id(outpad_portname2)))
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for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(outpad_portname2))))
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skip_wire_bits.insert(bit);
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if (cell->type == RTLIL::escape_id(inoutpad_celltype) && cell->hasPort(RTLIL::escape_id(inoutpad_portname2)))
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for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(inoutpad_portname2))))
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skip_wire_bits.insert(bit);
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if (cell->type == RTLIL::escape_id(toutpad_celltype) && cell->hasPort(RTLIL::escape_id(toutpad_portname3)))
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for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(toutpad_portname3))))
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skip_wire_bits.insert(bit);
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if (cell->type == RTLIL::escape_id(tinoutpad_celltype) && cell->hasPort(RTLIL::escape_id(tinoutpad_portname4)))
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for (auto bit : sigmap(cell->getPort(RTLIL::escape_id(tinoutpad_portname4))))
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skip_wire_bits.insert(bit);
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}
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if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
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{
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dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
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pool<pair<IdString, IdString>> norewrites;
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SigMap rewrites;
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for (auto cell : module->cells())
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if (cell->type == "$_TBUF_") {
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SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
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tbuf_bits[bit].first = cell->name;
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}
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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for (auto bit : sigmap(port.second))
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if (tbuf_bits.count(bit))
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tbuf_bits.at(bit).second.insert(cell->name);
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for (auto wire : module->selected_wires())
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{
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if (!wire->port_output)
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continue;
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wire_bit(wire, i);
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SigBit mapped_wire_bit = sigmap(wire_bit);
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if (tbuf_bits.count(mapped_wire_bit) == 0)
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continue;
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if (skip_wire_bits.count(mapped_wire_bit))
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continue;
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auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
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Cell *tbuf_cell = module->cell(tbuf_cache.first);
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if (tbuf_cell == nullptr)
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continue;
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SigBit en_sig = tbuf_cell->getPort("\\E").as_bit();
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SigBit data_sig = tbuf_cell->getPort("\\A").as_bit();
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if (wire->port_input && !tinoutpad_celltype.empty())
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{
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log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
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Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
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Wire *owire = module->addWire(NEW_ID);
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cell->setPort(RTLIL::escape_id(tinoutpad_portname), en_sig);
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cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
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cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
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cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
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cell->attributes["\\keep"] = RTLIL::Const(1);
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for (auto cn : tbuf_cache.second) {
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auto c = module->cell(cn);
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if (c == nullptr)
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continue;
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for (auto port : c->connections()) {
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SigSpec sig = port.second;
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bool newsig = false;
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for (auto &bit : sig)
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if (sigmap(bit) == mapped_wire_bit) {
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bit = owire;
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newsig = true;
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}
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if (newsig)
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c->setPort(port.first, sig);
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}
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}
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module->remove(tbuf_cell);
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skip_wires[wire->name].insert(i);
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norewrites.insert(make_pair(cell->name, RTLIL::escape_id(tinoutpad_portname4)));
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rewrites.add(sigmap(wire_bit), owire);
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continue;
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}
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if (!wire->port_input && !toutpad_celltype.empty())
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{
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log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
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Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
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cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
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cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
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cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
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cell->attributes["\\keep"] = RTLIL::Const(1);
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for (auto cn : tbuf_cache.second) {
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auto c = module->cell(cn);
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if (c == nullptr)
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continue;
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for (auto port : c->connections()) {
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SigSpec sig = port.second;
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bool newsig = false;
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for (auto &bit : sig)
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if (sigmap(bit) == mapped_wire_bit) {
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bit = data_sig;
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newsig = true;
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}
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if (newsig)
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c->setPort(port.first, sig);
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}
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}
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module->remove(tbuf_cell);
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skip_wires[wire->name].insert(i);
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continue;
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}
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}
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}
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if (GetSize(norewrites))
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{
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for (auto cell : module->cells())
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for (auto port : cell->connections())
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{
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if (norewrites.count(make_pair(cell->name, port.first)))
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continue;
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SigSpec orig_sig = sigmap(port.second);
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SigSpec new_sig = rewrites(orig_sig);
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if (orig_sig != new_sig)
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cell->setPort(port.first, new_sig);
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}
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}
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}
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for (auto wire : module->selected_wires())
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{
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if (!wire->port_id)
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continue;
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std::string celltype, portname, portname2;
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pool<int> skip_bit_indices;
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if (skip_wires.count(wire->name)) {
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if (!flag_bits)
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continue;
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skip_bit_indices = skip_wires.at(wire->name);
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}
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for (int i = 0; i < GetSize(wire); i++)
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if (skip_wire_bits.count(sigmap(SigBit(wire, i))))
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skip_bit_indices.insert(i);
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if (GetSize(wire) == GetSize(skip_bit_indices))
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continue;
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if (wire->port_input && !wire->port_output) {
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if (inpad_celltype.empty()) {
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log("Don't map input port %s.%s: Missing option -inpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = inpad_celltype;
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portname = inpad_portname;
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portname2 = inpad_portname2;
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} else
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if (!wire->port_input && wire->port_output) {
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if (outpad_celltype.empty()) {
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log("Don't map output port %s.%s: Missing option -outpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = outpad_celltype;
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portname = outpad_portname;
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portname2 = outpad_portname2;
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} else
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if (wire->port_input && wire->port_output) {
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if (inoutpad_celltype.empty()) {
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log("Don't map inout port %s.%s: Missing option -inoutpad.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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celltype = inoutpad_celltype;
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portname = inoutpad_portname;
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portname2 = inoutpad_portname2;
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} else
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log_abort();
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if (!flag_bits && wire->width != 1 && widthparam.empty()) {
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log("Don't map multi-bit port %s.%s: Missing option -widthparam or -bits.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name));
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continue;
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}
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log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str());
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RTLIL::Wire *new_wire = NULL;
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if (!portname2.empty()) {
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new_wire = module->addWire(NEW_ID, wire);
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module->swap_names(new_wire, wire);
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wire->attributes.clear();
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}
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if (flag_bits)
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{
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for (int i = 0; i < wire->width; i++)
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{
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if (skip_bit_indices.count(i)) {
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if (wire->port_output)
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module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
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else
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module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
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continue;
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}
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RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
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cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
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if (!portname2.empty())
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cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
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if (!widthparam.empty())
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cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
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if (!nameparam.empty())
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cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
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cell->attributes["\\keep"] = RTLIL::Const(1);
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}
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}
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else
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{
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RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
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cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
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if (!portname2.empty())
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cell->setPort(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
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if (!widthparam.empty())
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cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
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if (!nameparam.empty())
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cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
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cell->attributes["\\keep"] = RTLIL::Const(1);
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}
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wire->port_id = 0;
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wire->port_input = false;
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wire->port_output = false;
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}
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module->fixup_ports();
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}
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}
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} IopadmapPass;
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PRIVATE_NAMESPACE_END
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