mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
3aa4484a3c
o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
605 lines
15 KiB
C++
605 lines
15 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ExtractFaConfig
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{
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bool enable_fa = false;
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bool enable_ha = false;
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bool verbose = false;
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int maxdepth = 20;
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int maxbreadth = 6;
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};
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// http://svn.clifford.at/handicraft/2016/bindec/bindec.c
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int bindec(unsigned char v)
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{
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int r = v & 1;
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r += (~((v & 2) - 1)) & 10;
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r += (~((v & 4) - 1)) & 100;
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r += (~((v & 8) - 1)) & 1000;
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r += (~((v & 16) - 1)) & 10000;
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r += (~((v & 32) - 1)) & 100000;
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r += (~((v & 64) - 1)) & 1000000;
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r += (~((v & 128) - 1)) & 10000000;
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return r;
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}
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struct ExtractFaWorker
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{
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const ExtractFaConfig &config;
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Module *module;
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ConstEval ce;
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SigMap &sigmap;
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dict<SigBit, Cell*> driver;
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pool<SigBit> handled_bits;
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const int xor2_func = 0x6, xnor2_func = 0x9;
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const int xor3_func = 0x96, xnor3_func = 0x69;
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pool<tuple<SigBit, SigBit>> xorxnor2;
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pool<tuple<SigBit, SigBit, SigBit>> xorxnor3;
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dict<tuple<SigBit, SigBit>, dict<int, pool<SigBit>>> func2;
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dict<tuple<SigBit, SigBit, SigBit>, dict<int, pool<SigBit>>> func3;
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int count_func2;
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int count_func3;
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struct func2_and_info_t {
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bool inv_a, inv_b, inv_y;
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};
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struct func3_maj_info_t {
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bool inv_a, inv_b, inv_c, inv_y;
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};
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dict<int, func2_and_info_t> func2_and_info;
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dict<int, func3_maj_info_t> func3_maj_info;
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ExtractFaWorker(const ExtractFaConfig &config, Module *module) :
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config(config), module(module), ce(module), sigmap(ce.assign_map)
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{
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_",
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"$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_",
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"$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
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{
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SigBit y = sigmap(SigBit(cell->getPort("\\Y")));
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log_assert(driver.count(y) == 0);
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driver[y] = cell;
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}
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}
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for (int ia = 0; ia < 2; ia++)
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for (int ib = 0; ib < 2; ib++)
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{
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func2_and_info_t f2i;
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f2i.inv_a = ia;
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f2i.inv_b = ib;
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f2i.inv_y = false;
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int func = 0;
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for (int i = 0; i < 4; i++)
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{
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bool a = (i & 1) ? !f2i.inv_a : f2i.inv_a;
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bool b = (i & 2) ? !f2i.inv_b : f2i.inv_b;
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if (a && b) func |= 1 << i;
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}
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log_assert(func2_and_info.count(func) == 0);
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func2_and_info[func] = f2i;
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f2i.inv_y = true;
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func ^= 15;
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log_assert(func2_and_info.count(func) == 0);
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func2_and_info[func] = f2i;
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}
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for (int ia = 0; ia < 2; ia++)
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for (int ib = 0; ib < 2; ib++)
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for (int ic = 0; ic < 2; ic++)
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{
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func3_maj_info_t f3i;
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f3i.inv_a = ia;
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f3i.inv_b = ib;
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f3i.inv_c = ic;
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f3i.inv_y = false;
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int func = 0;
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for (int i = 0; i < 8; i++)
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{
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bool a = (i & 1) ? !f3i.inv_a : f3i.inv_a;
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bool b = (i & 2) ? !f3i.inv_b : f3i.inv_b;
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bool c = (i & 4) ? !f3i.inv_c : f3i.inv_c;
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if ((a && b) || (a && c) || (b &&c)) func |= 1 << i;
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}
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log_assert(func3_maj_info.count(func) == 0);
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func3_maj_info[func] = f3i;
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// f3i.inv_y = true;
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// func ^= 255;
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// log_assert(func3_maj_info.count(func) == 0);
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// func3_maj_info[func] = f3i;
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}
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}
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void check_partition(SigBit root, pool<SigBit> &leaves)
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{
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if (config.enable_ha && GetSize(leaves) == 2)
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{
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leaves.sort();
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SigBit A = SigSpec(leaves)[0];
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SigBit B = SigSpec(leaves)[1];
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int func = 0;
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for (int i = 0; i < 4; i++)
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{
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bool a_value = (i & 1) != 0;
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bool b_value = (i & 2) != 0;
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ce.push();
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ce.set(A, a_value ? State::S1 : State::S0);
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ce.set(B, b_value ? State::S1 : State::S0);
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SigSpec sig = root;
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if (!ce.eval(sig))
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log_abort();
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if (sig == State::S1)
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func |= 1 << i;
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ce.pop();
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}
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// log("%04d %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(root));
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if (func == xor2_func || func == xnor2_func)
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xorxnor2.insert(tuple<SigBit, SigBit>(A, B));
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count_func2++;
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func2[tuple<SigBit, SigBit>(A, B)][func].insert(root);
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}
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if (config.enable_fa && GetSize(leaves) == 3)
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{
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leaves.sort();
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SigBit A = SigSpec(leaves)[0];
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SigBit B = SigSpec(leaves)[1];
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SigBit C = SigSpec(leaves)[2];
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int func = 0;
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for (int i = 0; i < 8; i++)
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{
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bool a_value = (i & 1) != 0;
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bool b_value = (i & 2) != 0;
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bool c_value = (i & 4) != 0;
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ce.push();
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ce.set(A, a_value ? State::S1 : State::S0);
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ce.set(B, b_value ? State::S1 : State::S0);
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ce.set(C, c_value ? State::S1 : State::S0);
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SigSpec sig = root;
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if (!ce.eval(sig))
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log_abort();
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if (sig == State::S1)
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func |= 1 << i;
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ce.pop();
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}
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// log("%08d %s %s %s -> %s\n", bindec(func), log_signal(A), log_signal(B), log_signal(C), log_signal(root));
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if (func == xor3_func || func == xnor3_func)
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xorxnor3.insert(tuple<SigBit, SigBit, SigBit>(A, B, C));
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count_func3++;
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func3[tuple<SigBit, SigBit, SigBit>(A, B, C)][func].insert(root);
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}
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}
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void find_partitions(SigBit root, pool<SigBit> &leaves, pool<pool<SigBit>> &cache, int maxdepth, int maxbreadth)
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{
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if (cache.count(leaves))
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return;
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// log("%*s[%d] %s:", 20-maxdepth, "", maxdepth, log_signal(root));
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// for (auto bit : leaves)
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// log(" %s", log_signal(bit));
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// log("\n");
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cache.insert(leaves);
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check_partition(root, leaves);
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if (maxdepth == 0)
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return;
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for (SigBit bit : leaves)
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{
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if (driver.count(bit) == 0)
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continue;
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Cell *cell = driver.at(bit);
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pool<SigBit> new_leaves = leaves;
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new_leaves.erase(bit);
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if (cell->hasPort("\\A")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\A"))));
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if (cell->hasPort("\\B")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\B"))));
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if (cell->hasPort("\\C")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\C"))));
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if (cell->hasPort("\\D")) new_leaves.insert(sigmap(SigBit(cell->getPort("\\D"))));
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if (GetSize(new_leaves) > maxbreadth)
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continue;
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find_partitions(root, new_leaves, cache, maxdepth-1, maxbreadth);
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}
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}
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void assign_new_driver(SigBit bit, SigBit new_driver)
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{
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Cell *cell = driver.at(bit);
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if (sigmap(cell->getPort("\\Y")) == bit) {
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cell->setPort("\\Y", module->addWire(NEW_ID));
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module->connect(bit, new_driver);
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}
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}
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void run()
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{
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log("Extracting full/half adders from %s:\n", log_id(module));
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for (auto it : driver)
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{
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if (it.second->type.in("$_BUF_", "$_NOT_"))
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continue;
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SigBit root = it.first;
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pool<SigBit> leaves = { root };
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pool<pool<SigBit>> cache;
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if (config.verbose)
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log(" checking %s\n", log_signal(it.first));
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count_func2 = 0;
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count_func3 = 0;
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find_partitions(root, leaves, cache, config.maxdepth, config.maxbreadth);
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if (config.verbose && count_func2 > 0)
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log(" extracted %d two-input functions\n", count_func2);
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if (config.verbose && count_func3 > 0)
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log(" extracted %d three-input functions\n", count_func3);
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}
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for (auto &key : xorxnor3)
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{
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SigBit A = get<0>(key);
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SigBit B = get<1>(key);
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SigBit C = get<2>(key);
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log(" 3-Input XOR/XNOR %s %s %s:\n", log_signal(A), log_signal(B), log_signal(C));
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for (auto &it : func3.at(key))
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{
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if (it.first != xor3_func && it.first != xnor3_func)
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continue;
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log(" %08d ->", bindec(it.first));
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for (auto bit : it.second)
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log(" %s", log_signal(bit));
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log("\n");
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}
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dict<int, tuple<SigBit, SigBit, Cell*>> facache;
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for (auto &it : func3_maj_info)
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{
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int func = it.first;
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auto f3i = it.second;
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if (func3.at(key).count(func) == 0)
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continue;
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if (func3.at(key).count(xor3_func) == 0 && func3.at(key).count(xnor3_func) != 0) {
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f3i.inv_a = !f3i.inv_a;
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f3i.inv_b = !f3i.inv_b;
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f3i.inv_c = !f3i.inv_c;
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f3i.inv_y = !f3i.inv_y;
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}
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if (!f3i.inv_a && !f3i.inv_b && !f3i.inv_c && !f3i.inv_y) {
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log(" Majority without inversions:\n");
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} else {
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log(" Majority with inverted");
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if (f3i.inv_a) log(" A");
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if (f3i.inv_b) log(" B");
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if (f3i.inv_c) log(" C");
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if (f3i.inv_y) log(" Y");
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log(":\n");
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}
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log(" %08d ->", bindec(func));
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for (auto bit : func3.at(key).at(func))
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log(" %s", log_signal(bit));
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log("\n");
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int fakey = 0;
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if (f3i.inv_a) fakey |= 1;
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if (f3i.inv_b) fakey |= 2;
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if (f3i.inv_c) fakey |= 4;
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int fakey_inv = fakey ^ 7;
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bool invert_xy = false;
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SigBit X, Y;
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if (facache.count(fakey))
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{
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auto &fa = facache.at(fakey);
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X = get<0>(fa);
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Y = get<1>(fa);
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log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
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}
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else
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if (facache.count(fakey_inv))
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{
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auto &fa = facache.at(fakey_inv);
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invert_xy = true;
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X = get<0>(fa);
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Y = get<1>(fa);
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log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
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}
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else
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{
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Cell *cell = module->addCell(NEW_ID, "$fa");
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cell->setParam("\\WIDTH", 1);
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log(" Created $fa cell %s.\n", log_id(cell));
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cell->setPort("\\A", f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
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cell->setPort("\\B", f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
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cell->setPort("\\C", f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
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X = module->addWire(NEW_ID);
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Y = module->addWire(NEW_ID);
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cell->setPort("\\X", X);
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cell->setPort("\\Y", Y);
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facache[fakey] = make_tuple(X, Y, cell);
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}
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if (func3.at(key).count(xor3_func)) {
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SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
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for (auto bit : func3.at(key).at(xor3_func))
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assign_new_driver(bit, YY);
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}
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if (func3.at(key).count(xnor3_func)) {
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SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
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for (auto bit : func3.at(key).at(xnor3_func))
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assign_new_driver(bit, YY);
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}
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SigBit XX = invert_xy != f3i.inv_y ? module->NotGate(NEW_ID, X) : X;
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for (auto bit : func3.at(key).at(func))
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assign_new_driver(bit, XX);
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}
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}
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for (auto &key : xorxnor2)
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{
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SigBit A = get<0>(key);
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SigBit B = get<1>(key);
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log(" 2-Input XOR/XNOR %s %s:\n", log_signal(A), log_signal(B));
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for (auto &it : func2.at(key))
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{
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if (it.first != xor2_func && it.first != xnor2_func)
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continue;
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log(" %04d ->", bindec(it.first));
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for (auto bit : it.second)
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log(" %s", log_signal(bit));
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log("\n");
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}
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dict<int, tuple<SigBit, SigBit, Cell*>> facache;
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for (auto &it : func2_and_info)
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{
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int func = it.first;
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auto &f2i = it.second;
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if (func2.at(key).count(func) == 0)
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continue;
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if (!f2i.inv_a && !f2i.inv_b && !f2i.inv_y) {
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log(" AND without inversions:\n");
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} else {
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log(" AND with inverted");
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if (f2i.inv_a) log(" A");
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if (f2i.inv_b) log(" B");
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if (f2i.inv_y) log(" Y");
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log(":\n");
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}
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log(" %04d ->", bindec(func));
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for (auto bit : func2.at(key).at(func))
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log(" %s", log_signal(bit));
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log("\n");
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int fakey = 0;
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if (f2i.inv_a) fakey |= 1;
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if (f2i.inv_b) fakey |= 2;
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int fakey_inv = fakey ^ 3;
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bool invert_xy = false;
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SigBit X, Y;
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if (facache.count(fakey))
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{
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auto &fa = facache.at(fakey);
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X = get<0>(fa);
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Y = get<1>(fa);
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log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
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}
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else
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if (facache.count(fakey_inv))
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{
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auto &fa = facache.at(fakey_inv);
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invert_xy = true;
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X = get<0>(fa);
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Y = get<1>(fa);
|
|
log(" Reusing $fa cell %s.\n", log_id(get<2>(fa)));
|
|
}
|
|
else
|
|
{
|
|
Cell *cell = module->addCell(NEW_ID, "$fa");
|
|
cell->setParam("\\WIDTH", 1);
|
|
|
|
log(" Created $fa cell %s.\n", log_id(cell));
|
|
|
|
cell->setPort("\\A", f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
|
|
cell->setPort("\\B", f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
|
|
cell->setPort("\\C", State::S0);
|
|
|
|
X = module->addWire(NEW_ID);
|
|
Y = module->addWire(NEW_ID);
|
|
|
|
cell->setPort("\\X", X);
|
|
cell->setPort("\\Y", Y);
|
|
}
|
|
|
|
if (func2.at(key).count(xor2_func)) {
|
|
SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
|
|
for (auto bit : func2.at(key).at(xor2_func))
|
|
assign_new_driver(bit, YY);
|
|
}
|
|
|
|
if (func2.at(key).count(xnor2_func)) {
|
|
SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
|
|
for (auto bit : func2.at(key).at(xnor2_func))
|
|
assign_new_driver(bit, YY);
|
|
}
|
|
|
|
SigBit XX = invert_xy != f2i.inv_y ? module->NotGate(NEW_ID, X) : X;
|
|
|
|
for (auto bit : func2.at(key).at(func))
|
|
assign_new_driver(bit, XX);
|
|
}
|
|
}
|
|
}
|
|
};
|
|
|
|
struct ExtractFaPass : public Pass {
|
|
ExtractFaPass() : Pass("extract_fa", "find and extract full/half adders") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" extract_fa [options] [selection]\n");
|
|
log("\n");
|
|
log("This pass extracts full/half adders from a gate-level design.\n");
|
|
log("\n");
|
|
log(" -fa, -ha\n");
|
|
log(" Enable cell types (fa=full adder, ha=half adder)\n");
|
|
log(" All types are enabled if none of this options is used\n");
|
|
log("\n");
|
|
log(" -d <int>\n");
|
|
log(" Set maximum depth for extracted logic cones (default=20)\n");
|
|
log("\n");
|
|
log(" -b <int>\n");
|
|
log(" Set maximum breadth for extracted logic cones (default=6)\n");
|
|
log("\n");
|
|
log(" -v\n");
|
|
log(" Verbose output\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
ExtractFaConfig config;
|
|
|
|
log_header(design, "Executing EXTRACT_FA pass (find and extract full/half adders).\n");
|
|
log_push();
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-fa") {
|
|
config.enable_fa = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-ha") {
|
|
config.enable_ha = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-v") {
|
|
config.verbose = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-d" && argidx+2 < args.size()) {
|
|
config.maxdepth = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-b" && argidx+2 < args.size()) {
|
|
config.maxbreadth = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
if (!config.enable_fa && !config.enable_ha) {
|
|
config.enable_fa = true;
|
|
config.enable_ha = true;
|
|
}
|
|
|
|
for (auto module : design->selected_modules())
|
|
{
|
|
ExtractFaWorker worker(config, module);
|
|
worker.run();
|
|
}
|
|
|
|
log_pop();
|
|
}
|
|
} ExtractFaPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|