mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
3aa4484a3c
o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
379 lines
14 KiB
C++
379 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "passes/techmap/simplemap.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Dff2dffeWorker
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{
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const dict<IdString, IdString> &direct_dict;
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RTLIL::Module *module;
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SigMap sigmap;
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CellTypes ct;
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typedef std::pair<RTLIL::Cell*, int> cell_int_t;
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std::map<RTLIL::SigBit, cell_int_t> bit2mux;
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std::vector<RTLIL::Cell*> dff_cells;
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std::map<RTLIL::SigBit, int> bitusers;
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typedef std::map<RTLIL::SigBit, bool> pattern_t;
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typedef std::set<pattern_t> patterns_t;
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Dff2dffeWorker(RTLIL::Module *module, const dict<IdString, IdString> &direct_dict) :
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direct_dict(direct_dict), module(module), sigmap(module), ct(module->design)
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{
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for (auto wire : module->wires()) {
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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bitusers[bit]++;
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}
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for (auto cell : module->cells()) {
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if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") {
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RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
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for (int i = 0; i < GetSize(sig_y); i++)
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bit2mux[sig_y[i]] = cell_int_t(cell, i);
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}
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if (direct_dict.empty()) {
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if (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
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dff_cells.push_back(cell);
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} else {
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if (direct_dict.count(cell->type))
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dff_cells.push_back(cell);
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}
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for (auto conn : cell->connections()) {
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if (ct.cell_output(cell->type, conn.first))
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continue;
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for (auto bit : sigmap(conn.second))
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bitusers[bit]++;
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}
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}
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}
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patterns_t find_muxtree_feedback_patterns(RTLIL::SigBit d, RTLIL::SigBit q, pattern_t path)
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{
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patterns_t ret;
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if (d == q) {
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ret.insert(path);
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return ret;
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}
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if (bit2mux.count(d) == 0 || bitusers[d] > 1)
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return ret;
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cell_int_t mux_cell_int = bit2mux.at(d);
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RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort("\\A"));
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RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort("\\B"));
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RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort("\\S"));
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int width = GetSize(sig_a), index = mux_cell_int.second;
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for (int i = 0; i < GetSize(sig_s); i++)
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if (path.count(sig_s[i]) && path.at(sig_s[i]))
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{
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ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
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if (sig_b[i*width + index] == q) {
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RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B");
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s[i*width + index] = RTLIL::Sx;
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mux_cell_int.first->setPort("\\B", s);
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}
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return ret;
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}
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pattern_t path_else = path;
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for (int i = 0; i < GetSize(sig_s); i++)
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{
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if (path.count(sig_s[i]))
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continue;
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pattern_t path_this = path;
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path_else[sig_s[i]] = false;
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path_this[sig_s[i]] = true;
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for (auto &pat : find_muxtree_feedback_patterns(sig_b[i*width + index], q, path_this))
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ret.insert(pat);
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if (sig_b[i*width + index] == q) {
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RTLIL::SigSpec s = mux_cell_int.first->getPort("\\B");
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s[i*width + index] = RTLIL::Sx;
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mux_cell_int.first->setPort("\\B", s);
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}
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}
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for (auto &pat : find_muxtree_feedback_patterns(sig_a[index], q, path_else))
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ret.insert(pat);
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if (sig_a[index] == q) {
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RTLIL::SigSpec s = mux_cell_int.first->getPort("\\A");
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s[index] = RTLIL::Sx;
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mux_cell_int.first->setPort("\\A", s);
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}
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return ret;
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}
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void simplify_patterns(patterns_t&)
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{
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// TBD
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}
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RTLIL::SigSpec make_patterns_logic(patterns_t patterns, bool make_gates)
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{
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RTLIL::SigSpec or_input;
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for (auto pat : patterns)
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{
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RTLIL::SigSpec s1, s2;
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for (auto it : pat) {
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s1.append(it.first);
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s2.append(it.second);
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}
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RTLIL::SigSpec y = module->addWire(NEW_ID);
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RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y);
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if (make_gates) {
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simplemap(module, c);
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module->remove(c);
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}
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or_input.append(y);
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}
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if (GetSize(or_input) == 0)
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return RTLIL::S1;
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if (GetSize(or_input) == 1)
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return or_input;
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RTLIL::SigSpec y = module->addWire(NEW_ID);
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RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
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if (make_gates) {
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simplemap(module, c);
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module->remove(c);
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}
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return y;
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}
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void handle_dff_cell(RTLIL::Cell *dff_cell)
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{
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RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort("\\D"));
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RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort("\\Q"));
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std::map<patterns_t, std::set<int>> grouped_patterns;
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std::set<int> remaining_indices;
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for (int i = 0 ; i < GetSize(sig_d); i++) {
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patterns_t patterns = find_muxtree_feedback_patterns(sig_d[i], sig_q[i], pattern_t());
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if (!patterns.empty()) {
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simplify_patterns(patterns);
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grouped_patterns[patterns].insert(i);
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} else
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remaining_indices.insert(i);
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}
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for (auto &it : grouped_patterns) {
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RTLIL::SigSpec new_sig_d, new_sig_q;
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for (int i : it.second) {
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new_sig_d.append(sig_d[i]);
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new_sig_q.append(sig_q[i]);
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}
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if (!direct_dict.empty()) {
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log(" converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q));
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dff_cell->setPort("\\E", make_patterns_logic(it.first, true));
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dff_cell->type = direct_dict.at(dff_cell->type);
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} else
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if (dff_cell->type == "$dff") {
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RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort("\\CLK"), make_patterns_logic(it.first, false),
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new_sig_d, new_sig_q, dff_cell->getParam("\\CLK_POLARITY").as_bool(), true);
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log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
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} else {
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RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort("\\C"), make_patterns_logic(it.first, true),
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new_sig_d, new_sig_q, dff_cell->type == "$_DFF_P_", true);
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log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
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}
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}
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if (!direct_dict.empty())
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return;
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if (remaining_indices.empty()) {
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log(" removing now obsolete cell %s.\n", log_id(dff_cell));
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module->remove(dff_cell);
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} else if (GetSize(remaining_indices) != GetSize(sig_d)) {
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log(" removing %d now obsolete bits from cell %s.\n", GetSize(sig_d) - GetSize(remaining_indices), log_id(dff_cell));
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RTLIL::SigSpec new_sig_d, new_sig_q;
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for (int i : remaining_indices) {
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new_sig_d.append(sig_d[i]);
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new_sig_q.append(sig_q[i]);
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}
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dff_cell->setPort("\\D", new_sig_d);
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dff_cell->setPort("\\Q", new_sig_q);
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dff_cell->setParam("\\WIDTH", GetSize(remaining_indices));
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}
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}
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void run()
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{
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log("Transforming FF to FF+Enable cells in module %s:\n", log_id(module));
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for (auto dff_cell : dff_cells) {
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// log("Handling candidate %s:\n", log_id(dff_cell));
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handle_dff_cell(dff_cell);
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}
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}
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};
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struct Dff2dffePass : public Pass {
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Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" dff2dffe [options] [selection]\n");
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log("\n");
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log("This pass transforms $dff cells driven by a tree of multiplexers with one or\n");
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log("more feedback paths to $dffe cells. It also works on gate-level cells such as\n");
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log("$_DFF_P_, $_DFF_N_ and $_MUX_.\n");
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log("\n");
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log(" -unmap\n");
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log(" operate in the opposite direction: replace $dffe cells with combinations\n");
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log(" of $dff and $mux cells. the options below are ignore in unmap mode.\n");
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log("\n");
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log(" -direct <internal_gate_type> <external_gate_type>\n");
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log(" map directly to external gate type. <internal_gate_type> can\n");
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log(" be any internal gate-level FF cell (except $_DFFE_??_). the\n");
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log(" <external_gate_type> is the cell type name for a cell with an\n");
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log(" identical interface to the <internal_gate_type>, except it\n");
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log(" also has an high-active enable port 'E'.\n");
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log(" Usually <external_gate_type> is an intermediate cell type\n");
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log(" that is then translated to the final type using 'techmap'.\n");
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log("\n");
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log(" -direct-match <pattern>\n");
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log(" like -direct for all DFF cell types matching the expression.\n");
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log(" this will use $__DFFE_* as <external_gate_type> matching the\n");
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log(" internal gate type $_DFF_*_, and $__DFFSE_* for those matching\n");
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log(" $_DFFS_*_, except for $_DFF_[NP]_, which is converted to \n");
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log(" $_DFFE_[NP]_.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
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bool unmap_mode = false;
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dict<IdString, IdString> direct_dict;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-unmap") {
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unmap_mode = true;
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continue;
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}
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if (args[argidx] == "-direct" && argidx + 2 < args.size()) {
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string direct_from = RTLIL::escape_id(args[++argidx]);
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string direct_to = RTLIL::escape_id(args[++argidx]);
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direct_dict[direct_from] = direct_to;
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continue;
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}
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if (args[argidx] == "-direct-match" && argidx + 1 < args.size()) {
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bool found_match = false;
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const char *pattern = args[++argidx].c_str();
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if (patmatch(pattern, "$_DFF_P_" )) found_match = true, direct_dict["$_DFF_P_" ] = "$_DFFE_PP_";
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if (patmatch(pattern, "$_DFF_N_" )) found_match = true, direct_dict["$_DFF_N_" ] = "$_DFFE_NP_";
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if (patmatch(pattern, "$_DFF_NN0_")) found_match = true, direct_dict["$_DFF_NN0_"] = "$__DFFE_NN0";
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if (patmatch(pattern, "$_DFF_NN1_")) found_match = true, direct_dict["$_DFF_NN1_"] = "$__DFFE_NN1";
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if (patmatch(pattern, "$_DFF_NP0_")) found_match = true, direct_dict["$_DFF_NP0_"] = "$__DFFE_NP0";
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if (patmatch(pattern, "$_DFF_NP1_")) found_match = true, direct_dict["$_DFF_NP1_"] = "$__DFFE_NP1";
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if (patmatch(pattern, "$_DFF_PN0_")) found_match = true, direct_dict["$_DFF_PN0_"] = "$__DFFE_PN0";
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if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict["$_DFF_PN1_"] = "$__DFFE_PN1";
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if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict["$_DFF_PP0_"] = "$__DFFE_PP0";
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if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict["$_DFF_PP1_"] = "$__DFFE_PP1";
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if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict["$__DFFS_NN0_"] = "$__DFFSE_NN0";
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if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict["$__DFFS_NN1_"] = "$__DFFSE_NN1";
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if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict["$__DFFS_NP0_"] = "$__DFFSE_NP0";
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if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict["$__DFFS_NP1_"] = "$__DFFSE_NP1";
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if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict["$__DFFS_PN0_"] = "$__DFFSE_PN0";
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if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict["$__DFFS_PN1_"] = "$__DFFSE_PN1";
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if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict["$__DFFS_PP0_"] = "$__DFFSE_PP0";
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if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict["$__DFFS_PP1_"] = "$__DFFSE_PP1";
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if (!found_match)
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log_cmd_error("No cell types matched pattern '%s'.\n", pattern);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!direct_dict.empty()) {
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log("Selected cell types for direct conversion:\n");
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for (auto &it : direct_dict)
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log(" %s -> %s\n", log_id(it.first), log_id(it.second));
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}
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for (auto mod : design->selected_modules())
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if (!mod->has_processes_warn())
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{
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if (unmap_mode) {
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for (auto cell : mod->selected_cells()) {
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if (cell->type == "$dffe") {
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RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort("\\D")));
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mod->addDff(NEW_ID, cell->getPort("\\CLK"), tmp, cell->getPort("\\Q"), cell->getParam("\\CLK_POLARITY").as_bool());
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if (cell->getParam("\\EN_POLARITY").as_bool())
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mod->addMux(NEW_ID, cell->getPort("\\Q"), cell->getPort("\\D"), cell->getPort("\\EN"), tmp);
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else
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mod->addMux(NEW_ID, cell->getPort("\\D"), cell->getPort("\\Q"), cell->getPort("\\EN"), tmp);
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mod->remove(cell);
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continue;
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}
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if (cell->type.substr(0, 7) == "$_DFFE_") {
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bool clk_pol = cell->type.substr(7, 1) == "P";
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bool en_pol = cell->type.substr(8, 1) == "P";
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RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
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mod->addDff(NEW_ID, cell->getPort("\\C"), tmp, cell->getPort("\\Q"), clk_pol);
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if (en_pol)
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mod->addMux(NEW_ID, cell->getPort("\\Q"), cell->getPort("\\D"), cell->getPort("\\E"), tmp);
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else
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mod->addMux(NEW_ID, cell->getPort("\\D"), cell->getPort("\\Q"), cell->getPort("\\E"), tmp);
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mod->remove(cell);
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continue;
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}
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}
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continue;
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}
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Dff2dffeWorker worker(mod, direct_dict);
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worker.run();
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}
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}
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} Dff2dffePass;
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PRIVATE_NAMESPACE_END
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