Marcelina Kościelnicka 6cd135a5eb opt_expr: Remove -clkinv option, make it the default. ... Adds -noclkinv option just in case the old behavior was actually useful to someone.		2020-07-31 00:08:15 +02:00
..
.gitignore
abc9_dff.ys	abc9_ops: update messaging (credit to @Xiretza for spotting)	2020-05-30 08:57:48 -07:00
add_sub.ys
adffs.ys
attributes_test.ys
blockram.ys
bug1460.ys
bug1462.ys
bug1480.ys
bug1598.ys
bug1605.ys
counter.ys
dffs.ys
dsp_cascade.ys
dsp_fastfir.ys
dsp_simd.ys
fsm.ys	synth_xilinx: Use opt_dff.	2020-07-30 22:26:09 +02:00
latches.ys	opt_expr: Remove -clkinv option, make it the default.	2020-07-31 00:08:15 +02:00
logic.ys
lutram.ys
macc.sh
macc.v	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
macc.ys	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
macc_tb.v
mul.ys
mul_unsigned.v
mul_unsigned.ys
mux.ys	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
mux_lut4.ys
nosrl.ys	xilinx: Fix srl regression.	2020-07-12 23:41:27 +02:00
opt_lut_ins.ys
pmgen_xilinx_srl.ys	satgen: Add support for dffe, sdff, sdffe, sdffce cells.	2020-07-24 03:19:21 +02:00
run-test.sh
shifter.ys
tribuf.sh
tribuf.ys
xilinx_dffopt.ys	xilinx: xilinx_dffopt to read cells_sim.v; fix test	2020-04-22 16:25:23 -07:00
xilinx_dffopt_blacklist.txt
xilinx_dsp.ys	tests: read +/xilinx/cell_sim.v before xilinx_dsp test	2020-04-22 17:50:30 -07:00
xilinx_srl.v	tests: fix some test warnings	2020-05-25 10:07:58 -07:00
xilinx_srl.ys