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99 lines
3.6 KiB
Verilog
99 lines
3.6 KiB
Verilog
// The four D flip-flops (DFFs) in a Cyclone V/10GX Adaptive Logic Module (ALM)
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// act as one-bit memory cells that can be placed very flexibly (wherever there's
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// an ALM); each flop is represented by a MISTRAL_FF cell.
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//
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// The flops in these chips are rather flexible in some ways, but in practice
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// quite crippled by FPGA standards.
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//
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// What the flops can do
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// ---------------------
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// The core flop acts as a single-bit memory that initialises to zero at chip
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// reset. It takes in data on the rising edge of CLK if ENA is high,
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// and outputs it to Q. The ENA (clock enable) pin can therefore be used to
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// capture the input only if a condition is true.
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//
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// The data itself is zero if SCLR (synchronous clear) is high, else it comes
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// from SDATA (synchronous data) if SLOAD (synchronous load) is high, or DATAIN
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// if SLOAD is low.
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//
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// If ACLR (asynchronous clear) is low then Q is forced to zero, regardless of
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// the synchronous inputs or CLK edge. This is most often used for an FPGA-wide
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// power-on reset.
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//
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// An asynchronous set that sets Q to one can be emulated by inverting the input
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// and output of the flop, resulting in ACLR forcing Q to zero, which then gets
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// inverted to produce one. Likewise, logic can operate on the falling edge of
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// CLK if CLK is inverted before being passed as an input.
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//
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// What the flops *can't* do
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// -------------------------
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// The trickiest part of the above capabilities is the lack of configurable
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// initialisation state. For example, it isn't possible to implement a flop with
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// asynchronous clear that initialises to one, because the hardware initialises
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// to zero. Likewise, you can't emulate a flop with asynchronous set that
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// initialises to zero, because the inverters mean the flop initialises to one.
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//
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// If the input design requires one of these cells (which appears to be rare
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// in practice) then synth_intel_alm will fail to synthesize the design where
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// other Yosys synthesis scripts might succeed.
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//
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// This stands in notable contrast to e.g. Xilinx flip-flops, which have
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// configurable initialisation state and native synchronous/asynchronous
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// set/clear (although not at the same time), which means they can generally
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// implement a much wider variety of logic.
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// DATAIN: synchronous data input
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// CLK: clock input (positive edge)
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// ACLR: asynchronous clear (negative-true)
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// ENA: clock-enable
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// SCLR: synchronous clear
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// SLOAD: synchronous load
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// SDATA: synchronous load data
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//
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// Q: data output
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//
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// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.
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(* abc9_box, lib_whitebox *)
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module MISTRAL_FF(
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input DATAIN,
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(* clkbuf_sink *) input CLK,
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input ACLR, ENA, SCLR, SLOAD, SDATA,
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output reg Q
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);
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`ifdef cyclonev
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specify
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if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
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if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
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if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;
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$setup(DATAIN, posedge CLK, /* -196 */ 0);
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$setup(ENA, posedge CLK, /* -196 */ 0);
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$setup(SCLR, posedge CLK, /* -196 */ 0);
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$setup(SLOAD, posedge CLK, /* -196 */ 0);
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$setup(SDATA, posedge CLK, /* -196 */ 0);
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if (ACLR === 1'b0) (ACLR => Q) = 282;
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endspecify
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`endif
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initial begin
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// Altera flops initialise to zero.
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Q = 0;
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end
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always @(posedge CLK, negedge ACLR) begin
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// Asynchronous clear
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if (!ACLR) Q <= 0;
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// Clock-enable
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else if (ENA) begin
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// Synchronous clear
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if (SCLR) Q <= 0;
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// Synchronous load
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else if (SLOAD) Q <= SDATA;
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else Q <= DATAIN;
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end
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end
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endmodule
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