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https://github.com/YosysHQ/yosys
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133 lines
3.1 KiB
Verilog
133 lines
3.1 KiB
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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// DFF, asynchronous set/reset, enable
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module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q);
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input C;
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input S;
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input R;
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input E;
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input D;
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output Q;
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dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
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endmodule
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module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q);
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input C;
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input S;
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input R;
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input E;
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input D;
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output Q;
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dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
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endmodule
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// DFF, synchronous set or reset, enable
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module \$_SDFFE_PN0P_ (D, C, R, E, Q);
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input D;
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input C;
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input R;
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input E;
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output Q;
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sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
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endmodule
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module \$_SDFFE_PN1P_ (D, C, R, E, Q);
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input D;
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input C;
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input R;
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input E;
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output Q;
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sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
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endmodule
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module \$_SDFFE_NN0P_ (D, C, R, E, Q);
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input D;
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input C;
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input R;
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input E;
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output Q;
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sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1));
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endmodule
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module \$_SDFFE_NN1P_ (D, C, R, E, Q);
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input D;
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input C;
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input R;
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input E;
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output Q;
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sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R));
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endmodule
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// Latch, no set/reset, no enable
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module \$_DLATCH_P_ (input E, D, output Q);
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latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1));
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endmodule
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module \$_DLATCH_N_ (input E, D, output Q);
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latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1));
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endmodule
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// Latch with async set and reset and enable
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module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
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latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
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endmodule
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module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q);
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latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
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endmodule
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module \$__SHREG_DFF_P_ (D, Q, C);
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input D;
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input C;
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output Q;
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parameter DEPTH = 2;
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reg [DEPTH-2:0] q;
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genvar i;
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generate for (i = 0; i < DEPTH; i = i + 1) begin: slice
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// First in chain
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generate if (i == 0) begin
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sh_dff #() shreg_beg (
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.Q(q[i]),
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.D(D),
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.C(C)
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);
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end endgenerate
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// Middle in chain
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generate if (i > 0 && i != DEPTH-1) begin
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sh_dff #() shreg_mid (
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.Q(q[i]),
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.D(q[i-1]),
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.C(C)
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);
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end endgenerate
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// Last in chain
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generate if (i == DEPTH-1) begin
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sh_dff #() shreg_end (
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.Q(Q),
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.D(q[i-1]),
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.C(C)
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);
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end endgenerate
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end: slice
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endgenerate
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endmodule
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