mirror of
https://github.com/YosysHQ/yosys
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57 lines
1.4 KiB
Text
57 lines
1.4 KiB
Text
state <SigSpec> shiftxB
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match shiftx
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select shiftx->type == $shiftx
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select param(shiftx, \Y_WIDTH).as_int() > 1
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endmatch
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match macc
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select macc->type == $macc
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select param(macc, \B_WIDTH).as_int() == 0
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optional
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endmatch
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code shiftxB
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if (macc) {
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shiftxB = port(shiftx, \B);
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const int b_width = param(shiftx, \B_WIDTH).as_int();
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if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
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shiftxB = shiftxB.extract(0, b_width-1);
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if (port(macc, \Y) != shiftxB) {
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blacklist(shiftx);
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reject;
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}
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Const config = param(macc, \CONFIG);
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const int config_width = param(macc, \CONFIG_WIDTH).as_int();
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const int num_bits = config.extract(0, 4).as_int();
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const int num_ports = (config_width - 4) / (2 + 2*num_bits);
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if (num_ports != 1) {
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blacklist(shiftx);
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reject;
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}
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// IS_SIGNED?
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if (config[4] == 1) {
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blacklist(shiftx);
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reject;
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}
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// DO_SUBTRACT?
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if (config[5] == 1) {
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blacklist(shiftx);
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reject;
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}
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const int port_size_A = config.extract(6, num_bits).as_int();
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const int port_size_B = config.extract(6 + num_bits, num_bits).as_int();
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const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B);
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if (!port_B.is_fully_const()) {
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blacklist(shiftx);
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reject;
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}
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const int multiply_factor = port_B.as_int();
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if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) {
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blacklist(shiftx);
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reject;
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}
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shiftxB = port(macc, \A).extract(0, port_size_A);
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}
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endcode
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