mirror of
https://github.com/YosysHQ/yosys
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e40134c856
Add properties page, move cell_gate and cell_word under a singular cell_index along with properties. Fix links accordingly. Also drop x-aware and x-output todos since they are resolved. |
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| .. | ||
| APPNOTE_010_Verilog_to_BLIF.rst | ||
| APPNOTE_012_Verilog_to_BTOR.rst | ||
| auxlibs.rst | ||
| auxprogs.rst | ||
| env_vars.rst | ||
| primer.rst | ||
| rtlil_text.rst | ||