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.gitignore
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added more .gitignore files (make test)
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2013-01-05 11:35:52 +01:00 |
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aes_kexp128.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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always01.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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always02.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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always03.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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arraycells.v
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Fixed typo in tests/simple/arraycells.v
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2017-01-04 12:39:01 +01:00 |
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arrays01.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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arrays02.sv
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Add proper test for SV-style arrays
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2019-06-20 12:06:07 +02:00 |
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attrib01_module.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib02_port_decl.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib03_parameter.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib04_net_var.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib05_port_conn.v.DISABLED
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib06_operator_suffix.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib07_func_call.v.DISABLED
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib08_mod_inst.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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attrib09_case.v
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Added tests for attributes
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2019-06-03 09:25:20 +02:00 |
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carryadd.v
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Bugfix in name resolution with generate blocks
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2014-01-30 15:01:28 +01:00 |
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constmuldivmod.v
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Added opt_expr support for div/mod by power-of-two
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2016-05-29 12:17:36 +02:00 |
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constpower.v
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Fixed handling of power operator
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2013-11-07 22:20:00 +01:00 |
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defvalue.sv
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Add defvalue test, minor autotest fixes for .sv files
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2019-06-19 12:12:08 +02:00 |
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dff_different_styles.v
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Another block of spelling fixes
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2015-08-14 23:27:05 +02:00 |
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dff_init.v
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Add test case from #997
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2019-05-07 19:58:04 +02:00 |
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fiedler-cooley.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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forgen01.v
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Progress in Verific bindings
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2014-03-17 01:56:00 +01:00 |
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forgen02.v
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
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2013-03-31 11:17:56 +02:00 |
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forloops.v
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Add additional test cases for for-loops
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2019-05-01 09:32:07 +02:00 |
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fsm.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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generate.v
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Add test
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2019-06-20 16:07:22 -07:00 |
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graphtest.v
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Squelch trailing whitespace
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2017-04-12 15:11:09 +02:00 |
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hierarchy.v
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Another block of spelling fixes
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2015-08-14 23:27:05 +02:00 |
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hierdefparam.v
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Fix handling of defparam for when default_nettype is none
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2019-02-24 20:09:41 +01:00 |
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i2c_master_tests.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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implicit_ports.v
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Rename implicit_ports.sv test to implicit_ports.v
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2019-06-07 13:12:25 +02:00 |
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localparam_attr.v
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Added tests for Verilog frontent for attributes on parameters and localparams
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2019-05-16 12:53:43 +02:00 |
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loops.v
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
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macros.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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mem2reg.v
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Add splitcmplxassign test case and silence splitcmplxassign warning
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2019-05-01 10:01:54 +02:00 |
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mem_arst.v
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Make SV2017 compliant courtesy of @wsnyder
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2019-12-12 07:34:07 -08:00 |
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memory.v
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Fixed bug with memories that do not have a down-to-zero data width
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2016-08-22 14:27:46 +02:00 |
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multiplier.v
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Added multiplier test case from eda playground
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2013-12-18 13:43:53 +01:00 |
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muxtree.v
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improvements in muxtree/select_leaves test
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2015-01-18 13:24:01 +01:00 |
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omsp_dbg_uart.v
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
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operators.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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param_attr.v
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Added tests for Verilog frontent for attributes on parameters and localparams
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2019-05-16 12:53:43 +02:00 |
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paramods.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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partsel.v
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Added support for "upto" wires to Verilog front- and back-end
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2014-07-28 14:25:03 +02:00 |
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process.v
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Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
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2013-04-13 21:19:10 +02:00 |
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realexpr.v
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Add test case for real parameters
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2019-08-20 11:38:21 +02:00 |
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repwhile.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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retime.v
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Add retime test
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2019-04-05 16:28:46 -07:00 |
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rotate.v
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Another block of spelling fixes
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2015-08-14 23:27:05 +02:00 |
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run-test.sh
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Use command -v rather than which
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2019-09-03 00:57:32 +01:00 |
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scopes.v
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Improved scope resolution of local regs in Verilog+AST frontend
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2014-08-05 12:15:53 +02:00 |
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signedexpr.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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sincos.v
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Fix in sincos testbench gen
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2013-12-04 09:24:52 +01:00 |
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specify.v
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Fix tests/simple/specify.v
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2018-03-27 14:34:00 +02:00 |
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subbytes.v
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initial import
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2013-01-05 11:13:26 +01:00 |
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task_func.v
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Fix handling of task output ports in clocked always blocks, fixes #857
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2019-03-07 22:44:37 -08:00 |
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undef_eqx_nex.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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usb_phy_tests.v
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Renamed some of the test cases in tests/simple to avoid name collisions
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2014-07-25 13:01:45 +02:00 |
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values.v
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
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vloghammer.v
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Another block of spelling fixes
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2015-08-14 23:27:05 +02:00 |
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wandwor.v
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Add actual wandwor test that is part of "make test"
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2019-05-28 16:42:50 +02:00 |
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wreduce.v
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Improvements in wreduce
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2015-10-31 13:39:30 +01:00 |
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xfirrtl
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
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2019-07-31 09:27:38 -07:00 |
