mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 19:52:31 +00:00 
			
		
		
		
	This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
		
			
				
	
	
		
			30 lines
		
	
	
	
		
			659 B
		
	
	
	
		
			Systemverilog
		
	
	
	
	
	
			
		
		
	
	
			30 lines
		
	
	
	
		
			659 B
		
	
	
	
		
			Systemverilog
		
	
	
	
	
	
| `default_nettype none
 | |
| 
 | |
| module gate(out);
 | |
|     wire [3:0] x;
 | |
|     for (genvar x = 0; x < 2; x++) begin : blk
 | |
|         localparam w = x;
 | |
|         if (x == 0) begin : sub
 | |
|             wire [w:0] x;
 | |
|         end
 | |
|     end
 | |
|     assign x = 2;
 | |
|     assign blk[0].sub.x = '1;
 | |
|     output wire [9:0] out;
 | |
|     assign out = {1'bx, x, blk[0].sub.x};
 | |
| endmodule
 | |
| 
 | |
| module gold(out);
 | |
|     wire [3:0] x;
 | |
|     genvar z;
 | |
|     for (z = 0; z < 2; z++) begin : blk
 | |
|         localparam w = z;
 | |
|         if (z == 0) begin : sub
 | |
|             wire [w:0] x;
 | |
|         end
 | |
|     end
 | |
|     assign x = 2;
 | |
|     assign blk[0].sub.x = '1;
 | |
|     output wire [9:0] out;
 | |
|     assign out = {1'bx, x, blk[0].sub.x};
 | |
| endmodule
 |