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				https://github.com/YosysHQ/yosys
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	| This maps memories for a global clock based formal verification flow. This implies -keepdc, uses $ff cells for ROMs and sets hdlname attributes. | ||
|---|---|---|
| .. | ||
| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| pmgen | ||
| proc | ||
| sat | ||
| techmap | ||
| tests | ||