mirror of
https://github.com/YosysHQ/yosys
synced 2026-02-08 01:58:00 +00:00
fc56978703
The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680 |
||
|---|---|---|
| .. | ||
| achronix | ||
| anlogic | ||
| common | ||
| coolrunner2 | ||
| easic | ||
| ecp5 | ||
| efinix | ||
| fabulous | ||
| gatemate | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| intel_alm | ||
| machxo2 | ||
| nexus | ||
| quicklogic | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||