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20 lines
261 B
Verilog
20 lines
261 B
Verilog
module uut_forgen01(a, y);
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input [4:0] a;
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output y;
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integer i, j;
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reg [31:0] lut;
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initial begin
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for (i = 0; i < 32; i = i+1) begin
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lut[i] = i > 1;
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for (j = 2; j*j <= i; j = j+1)
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if (i % j == 0)
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lut[i] = 0;
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end
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end
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assign y = lut[a];
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endmodule
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