mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
efa278e232
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
283 lines
8.1 KiB
C++
283 lines
8.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ChformalPass : public Pass {
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ChformalPass() : Pass("chformal", "change formal constraints of the design") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" chformal [types] [mode] [options] [selection]\n");
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log("\n");
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log("Make changes to the formal constraints of the design. The [types] options\n");
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log("the type of constraint to operate on. If none of the following options are given,\n");
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log("the command will operate on all constraint types:\n");
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log("\n");
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log(" -assert $assert cells, representing assert(...) constraints\n");
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log(" -assume $assume cells, representing assume(...) constraints\n");
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log(" -live $live cells, representing assert(s_eventually ...)\n");
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log(" -fair $fair cells, representing assume(s_eventually ...)\n");
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log(" -cover $cover cells, representing cover() statements\n");
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log("\n");
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log("Exactly one of the following modes must be specified:\n");
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log("\n");
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log(" -remove\n");
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log(" remove the cells and thus constraints from the design\n");
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log("\n");
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log(" -early\n");
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log(" bypass FFs that only delay the activation of a constraint\n");
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log("\n");
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log(" -delay <N>\n");
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log(" delay activation of the constraint by <N> clock cycles\n");
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log("\n");
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log(" -skip <N>\n");
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log(" ignore activation of the constraint in the first <N> clock cycles\n");
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log("\n");
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log(" -assert2assume\n");
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log(" -assume2assert\n");
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log(" -live2fair\n");
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log(" -fair2live\n");
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log(" change the roles of cells as indicated. these options can be combined\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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bool assert2assume = false;
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bool assume2assert = false;
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bool live2fair = false;
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bool fair2live = false;
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pool<IdString> constr_types;
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char mode = 0;
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int mode_arg = 0;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-assert") {
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constr_types.insert("$assert");
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continue;
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}
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if (args[argidx] == "-assume") {
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constr_types.insert("$assume");
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continue;
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}
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if (args[argidx] == "-live") {
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constr_types.insert("$live");
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continue;
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}
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if (args[argidx] == "-fair") {
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constr_types.insert("$fair");
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continue;
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}
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if (args[argidx] == "-cover") {
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constr_types.insert("$cover");
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continue;
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}
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if (mode == 0 && args[argidx] == "-remove") {
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mode = 'r';
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continue;
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}
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if (mode == 0 && args[argidx] == "-early") {
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mode = 'e';
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continue;
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}
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if (mode == 0 && args[argidx] == "-delay" && argidx+1 < args.size()) {
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mode = 'd';
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mode_arg = atoi(args[++argidx].c_str());
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continue;
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}
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if (mode == 0 && args[argidx] == "-skip" && argidx+1 < args.size()) {
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mode = 's';
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mode_arg = atoi(args[++argidx].c_str());
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2assume") {
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assert2assume = true;
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mode = 'c';
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-assume2assert") {
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assume2assert = true;
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mode = 'c';
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-live2fair") {
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live2fair = true;
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mode = 'c';
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continue;
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}
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if ((mode == 0 || mode == 'c') && args[argidx] == "-fair2live") {
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fair2live = true;
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mode = 'c';
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (constr_types.empty()) {
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constr_types.insert("$assert");
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constr_types.insert("$assume");
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constr_types.insert("$live");
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constr_types.insert("$fair");
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constr_types.insert("$cover");
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}
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if (mode == 0)
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log_cmd_error("Mode option is missing.\n");
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for (auto module : design->selected_modules())
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{
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vector<Cell*> constr_cells;
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for (auto cell : module->selected_cells())
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if (constr_types.count(cell->type))
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constr_cells.push_back(cell);
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if (mode == 'r')
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{
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for (auto cell : constr_cells)
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module->remove(cell);
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}
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else
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if (mode == 'e')
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{
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SigMap sigmap(module);
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dict<SigBit, pair<SigBit, pair<SigBit, bool>>> ffmap;
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pool<SigBit> init_zero, init_one;
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for (auto wire : module->wires())
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{
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if (wire->attributes.count("\\init") == 0)
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continue;
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) {
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if (initval[i] == State::S0)
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init_zero.insert(initsig[i]);
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if (initval[i] == State::S1)
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init_one.insert(initsig[i]);
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}
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}
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$ff") {
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SigSpec D = sigmap(cell->getPort("\\D"));
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SigSpec Q = sigmap(cell->getPort("\\Q"));
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for (int i = 0; i < GetSize(D); i++)
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ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
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}
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if (cell->type == "$dff") {
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SigSpec D = sigmap(cell->getPort("\\D"));
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SigSpec Q = sigmap(cell->getPort("\\Q"));
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SigSpec C = sigmap(cell->getPort("\\CLK"));
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bool clockpol = cell->getParam("\\CLK_POLARITY").as_bool();
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for (int i = 0; i < GetSize(D); i++)
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ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol));
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}
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}
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for (auto cell : constr_cells)
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while (true)
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{
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SigSpec A = sigmap(cell->getPort("\\A"));
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SigSpec EN = sigmap(cell->getPort("\\EN"));
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if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
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break;
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if (!init_zero.count(EN)) {
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if (cell->type == "$cover") break;
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if (cell->type.in("$assert", "$assume") && !init_one.count(A)) break;
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}
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const auto &A_map = ffmap.at(A);
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const auto &EN_map = ffmap.at(EN);
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if (A_map.second != EN_map.second)
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break;
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cell->setPort("\\A", A_map.first);
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cell->setPort("\\EN", EN_map.first);
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}
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}
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else
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if (mode == 'd')
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{
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for (auto cell : constr_cells)
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for (int i = 0; i < mode_arg; i++)
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{
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SigSpec orig_a = cell->getPort("\\A");
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SigSpec orig_en = cell->getPort("\\EN");
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Wire *new_a = module->addWire(NEW_ID);
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Wire *new_en = module->addWire(NEW_ID);
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new_en->attributes["\\init"] = State::S0;
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module->addFf(NEW_ID, orig_a, new_a);
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module->addFf(NEW_ID, orig_en, new_en);
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cell->setPort("\\A", new_a);
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cell->setPort("\\EN", new_en);
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}
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}
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else
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if (mode == 's')
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{
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SigSpec en = State::S1;
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for (int i = 0; i < mode_arg; i++) {
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Wire *w = module->addWire(NEW_ID);
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w->attributes["\\init"] = State::S0;
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module->addFf(NEW_ID, en, w);
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en = w;
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}
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for (auto cell : constr_cells)
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cell->setPort("\\EN", module->LogicAnd(NEW_ID, en, cell->getPort("\\EN")));
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}
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else
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if (mode == 'c')
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{
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for (auto cell : constr_cells)
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if (assert2assume && cell->type == "$assert")
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cell->type = "$assume";
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else if (assume2assert && cell->type == "$assume")
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cell->type = "$assert";
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else if (live2fair && cell->type == "$live")
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cell->type = "$fair";
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else if (fair2live && cell->type == "$fair")
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cell->type = "$live";
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}
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}
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}
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} ChformalPass;
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PRIVATE_NAMESPACE_END
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