mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
efa278e232
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
121 lines
3.4 KiB
C++
121 lines
3.4 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include <string>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct TableBackend : public Backend {
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TableBackend() : Backend("table", "write design as connectivity table") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" write_table [options] [filename]\n");
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log("\n");
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log("Write the current design as connectivity table. The output is a tab-separated\n");
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log("ASCII table with the following columns:\n");
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log("\n");
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log(" module name\n");
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log(" cell name\n");
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log(" cell type\n");
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log(" cell port\n");
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log(" direction\n");
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log(" signal\n");
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log("\n");
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log("module inputs and outputs are output using cell type and port '-' and with\n");
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log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n");
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing TABLE backend.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-top" && argidx+1 < args.size()) {
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// top_module_name = args[++argidx];
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// continue;
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// }
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break;
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}
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extra_args(f, filename, args, argidx);
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design->sort();
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for (auto module : design->modules())
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{
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if (module->get_bool_attribute("\\blackbox"))
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continue;
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SigMap sigmap(module);
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for (auto wire : module->wires())
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{
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if (wire->port_id == 0)
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continue;
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*f << log_id(module) << "\t";
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*f << log_id(wire) << "\t";
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*f << "-" << "\t";
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*f << "-" << "\t";
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if (wire->port_input && wire->port_output)
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*f << "pio" << "\t";
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else if (wire->port_input)
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*f << "pi" << "\t";
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else if (wire->port_output)
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*f << "po" << "\t";
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else
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log_abort();
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*f << log_signal(sigmap(wire)) << "\n";
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}
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for (auto cell : module->cells())
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for (auto conn : cell->connections())
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{
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*f << log_id(module) << "\t";
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*f << log_id(cell) << "\t";
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*f << log_id(cell->type) << "\t";
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*f << log_id(conn.first) << "\t";
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if (cell->input(conn.first) && cell->output(conn.first))
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*f << "inout" << "\t";
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else if (cell->input(conn.first))
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*f << "in" << "\t";
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else if (cell->output(conn.first))
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*f << "out" << "\t";
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else
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*f << "unknown" << "\t";
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*f << log_signal(sigmap(conn.second)) << "\n";
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}
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}
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}
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} TableBackend;
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PRIVATE_NAMESPACE_END
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