mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
208 lines
7.2 KiB
C++
208 lines
7.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* (C) 2020 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef TIMINGINFO_H
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#define TIMINGINFO_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct TimingInfo
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{
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struct NameBit
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{
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RTLIL::IdString name;
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int offset;
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NameBit() : offset(0) {}
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NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
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explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
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bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
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bool operator!=(const NameBit& nb) const { return !operator==(nb); }
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std::optional<SigBit> get_connection(RTLIL::Cell *cell) {
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if (!cell->hasPort(name))
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return {};
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auto &port = cell->getPort(name);
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if (offset >= port.size())
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return {};
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return port[offset];
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}
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[[nodiscard]] Hasher hash_into(Hasher h) const {
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h.eat(name);
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h.eat(offset);
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return h;
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}
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};
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struct BitBit
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{
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NameBit first, second;
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BitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}
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BitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}
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bool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }
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[[nodiscard]] Hasher hash_into(Hasher h) const {
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h.eat(first);
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h.eat(second);
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return h;
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}
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};
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struct ModuleTiming
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{
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dict<BitBit, int> comb;
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dict<NameBit, std::pair<int,NameBit>> arrival, required;
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bool has_inputs;
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};
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dict<RTLIL::IdString, ModuleTiming> data;
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TimingInfo()
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{
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}
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TimingInfo(RTLIL::Design *design)
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{
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setup(design);
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}
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void setup(RTLIL::Design *design)
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{
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for (auto module : design->modules()) {
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if (!module->get_blackbox_attribute())
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continue;
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setup_module(module);
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}
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}
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const ModuleTiming& setup_module(RTLIL::Module *module)
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{
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auto r = data.insert(module->name);
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log_assert(r.second);
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auto &t = r.first->second;
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for (auto cell : module->cells()) {
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if (cell->type == ID($specify2)) {
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auto en = cell->getPort(ID::EN);
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if (en.is_fully_const() && !en.as_bool())
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continue;
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auto src = cell->getPort(ID::SRC);
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auto dst = cell->getPort(ID::DST);
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for (const auto &c : src.chunks())
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if (!c.wire || !c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dst.chunks())
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if (!c.wire || !c.wire->port_output)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
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int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
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int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
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int max = std::max(rise_max,fall_max);
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if (max < 0)
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log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
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if (cell->getParam(ID::FULL).as_bool()) {
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for (const auto &s : src)
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for (const auto &d : dst) {
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auto r = t.comb.insert(BitBit(s,d));
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if (!r.second)
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log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
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r.first->second = max;
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}
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}
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else {
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log_assert(GetSize(src) == GetSize(dst));
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for (auto i = 0; i < GetSize(src); i++) {
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const auto &s = src[i];
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const auto &d = dst[i];
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auto r = t.comb.insert(BitBit(s,d));
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if (!r.second)
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log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
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r.first->second = max;
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}
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}
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}
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else if (cell->type == ID($specify3)) {
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auto src = cell->getPort(ID::SRC).as_bit();
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auto dst = cell->getPort(ID::DST);
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if (!src.wire || !src.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dst.chunks())
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if (!c.wire->port_output)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
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int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
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int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
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int max = std::max(rise_max,fall_max);
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if (max < 0) {
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log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
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max = 0;
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}
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for (const auto &d : dst) {
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auto r = t.arrival.insert(NameBit(d));
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auto &v = r.first->second;
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if (r.second || v.first < max) {
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v.first = max;
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v.second = NameBit(src);
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}
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}
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}
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else if (cell->type == ID($specrule)) {
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IdString type = cell->getParam(ID::TYPE).decode_string();
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if (type != ID($setup) && type != ID($setuphold))
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continue;
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auto src = cell->getPort(ID::SRC);
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auto dst = cell->getPort(ID::DST).as_bit();
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for (const auto &c : src.chunks())
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if (!c.wire || !c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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if (!dst.wire || !dst.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
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int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
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if (max < 0) {
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log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
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max = 0;
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}
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for (const auto &s : src) {
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auto r = t.required.insert(NameBit(s));
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auto &v = r.first->second;
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if (r.second || v.first < max) {
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v.first = max;
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v.second = NameBit(dst);
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}
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}
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}
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}
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (wire->port_input) {
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t.has_inputs = true;
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break;
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}
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}
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return t;
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}
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decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
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decltype(data)::const_iterator end() const { return data.end(); }
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int count(RTLIL::IdString module_name) const { return data.count(module_name); }
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const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
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};
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YOSYS_NAMESPACE_END
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#endif
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