mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity
yosys/backends/cxxrtl
History
whitequark ef4e159447 cxxrtl: ignore cell input signedness when it is irrelevant. 
Before this commit, Verilog expressions like `x && 1` would result in
references to `logic_and_us` in generated CXXRTL code, which would
not compile. After this commit, since cells like that actually behave
the same regardless of signedness attributes, the signedness is
ignored, which also reduces the template instantiation pressure.
2020-06-09 07:26:13 +00:00
..
cxxrtl.h cxxrtl: ignore cell input signedness when it is irrelevant. 2020-06-09 07:26:13 +00:00
cxxrtl_backend.cc cxxrtl: ignore cell input signedness when it is irrelevant. 2020-06-09 07:26:13 +00:00
cxxrtl_capi.cc cxxrtl: add a C API for writing VCD dumps. 2020-06-07 03:48:00 +00:00
cxxrtl_capi.h cxxrtl: emit debug information for constant wires. 2020-06-08 17:29:08 +00:00
cxxrtl_vcd.h cxxrtl: don't check immutable values for changes in VCD writer. 2020-06-08 17:38:11 +00:00
cxxrtl_vcd_capi.cc cxxrtl: add a C API for writing VCD dumps. 2020-06-07 03:48:00 +00:00
cxxrtl_vcd_capi.h cxxrtl: add a C API for writing VCD dumps. 2020-06-07 03:48:00 +00:00
Makefile.inc cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc. 2020-06-07 03:48:40 +00:00