Martin Povišer ee3a4ce14d synth_lattice: Merge NOT gates on DFF control signals ... `dfflegalize` will emit NOT gates to drive control signals on flip-flops when mapping to supported flip-flop polarities. Typically in a design this will produce a number of NOT gates driven by the same signal. For one reason or another ABC doesn't fully cancel this redundancy during LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis QoR.		2023-11-07 16:21:39 +01:00
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achronix	Test fixes for latest iverilog	2022-09-21 15:46:43 +02:00
anlogic	anlogic: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
common	Merge pull request #3924 from andyfox-rushc/master	2023-09-18 16:46:59 +02:00
coolrunner2	Blackbox all whiteboxes after synthesis	2021-03-17 21:07:20 +00:00
easic	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
ecp5	Revert "ice40, ecp5: enable ABC9 by default"	2023-11-03 14:52:52 +00:00
efinix	efinix: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
fabulous	fabulous: Add support for LUT6s	2023-04-12 18:42:09 +02:00
gatemate	gatemate: Prevent implicit declaration of ram_{we,en}	2023-06-05 19:08:44 +02:00
gowin	gowin: fix abc9 attributes and specify blocks	2023-10-04 00:16:10 +01:00
greenpak4	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
ice40	Revert "ice40, ecp5: enable ABC9 by default"	2023-11-03 14:52:52 +00:00
intel	Fitting help messages to 80 character width	2022-08-24 10:40:57 +12:00
intel_alm	intel_alm: re-enable 8x40-bit M10K support	2023-05-29 06:42:03 +01:00
lattice	synth_lattice: Merge NOT gates on DFF control signals	2023-11-07 16:21:39 +01:00
nexus	nexus: Fix BRAM write enable in PDP mode	2023-01-04 17:59:36 +01:00
quicklogic	Fitting help messages to 80 character width	2022-08-24 10:40:57 +12:00
sf2	Test fixes for latest iverilog	2022-09-21 15:46:43 +02:00
xilinx	Update Xilinx cell definitions, fixes #3699	2023-03-23 09:44:36 +01:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00