3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
yosys/tests/verilog/genblk_wire.ys
Yannick Lamarre 702e1f2467 Add tests for implicit wires in generate blocks.
Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
2025-10-14 16:53:39 +02:00

16 lines
507 B
Text

#logger -expect warning "Identifier `\\genblk1[0].x' is implicitly declared." 1
#logger -expect warning "Identifier `\\genblk1[1].x' is implicitly declared." 1
read_verilog -sv genblk_wire.sv
select -assert-count 1 gate/genblk1[0].x
select -assert-count 1 gate/genblk1[1].x
select -assert-count 0 gate/genblk1[2].x
select -assert-count 1 gold/genblk1[0].x
select -assert-count 1 gold/genblk1[1].x
select -assert-count 0 gold/genblk1[2].x
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert