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9288889e20
Add simulation models, techmap, and dfflegalize rules for Gowin DL-series latch primitives. Latches use the same physical BEL as DFFs with REGMODE set to LATCH. All 12 variants are supported: DL, DLE, DLN, DLNE, DLC, DLCE, DLNC, DLNCE, DLP, DLPE, DLNP, DLNPE.
25 lines
901 B
Text
25 lines
901 B
Text
read_verilog ../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:DL
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DL t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:DLN
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select -assert-count 3 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DLN t:IBUF t:OBUF %% t:* %D
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