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https://github.com/YosysHQ/yosys
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edd8ff2c07
The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
31 lines
615 B
Bash
31 lines
615 B
Bash
#!/bin/bash
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set -ex
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rm -rf test_cells.tmp
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mkdir -p test_cells.tmp
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cd test_cells.tmp
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../../../yosys -p 'test_cell -n 5 -w test all /$alu /$fa /$lcu /$lut /$sop /$macc /$mul /$div /$mod /$divfloor /$modfloor'
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for fn in test_*.il; do
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../../../yosys -p "
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read_ilang $fn
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rename gold gate
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synth
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read_ilang $fn
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miter -equiv -make_assert -flatten gold gate main
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hierarchy -top main
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write_btor ${fn%.il}.btor
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"
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boolectormc -kmax 1 --trace-gen --stop-first -v ${fn%.il}.btor > ${fn%.il}.out
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if grep " SATISFIABLE" ${fn%.il}.out; then
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echo "Check failed for ${fn%.il}."
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exit 1
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fi
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done
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echo "OK."
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