mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-27 02:45:52 +00:00
ece25a45d4
Aggressive wire localization and inlining is necessary for CXXRTL to
achieve high performance. However, that comes with a cost: reduced
debug information coverage. Previously, as a workaround, the `-Og`
option could have been used to guarantee complete coverage, at a cost
of a significant performance penalty.
This commit introduces debug information outlining. The main eval()
function is compiled with the user-specified optimization settings.
In tandem, an auxiliary debug_eval() function, compiled from the same
netlist, can be used to reconstruct the values of localized/inlined
signals on demand. To the extent that it is possible, debug_eval()
reuses the results of computations performed by eval(), only filling
in the missing values.
Benchmarking a representative design (Minerva SoC SRAM) shows that:
* Switching from `-O4`/`-Og` to `-O6` reduces runtime by ~40%.
* Switching from `-g1` to `-g2`, both used with `-O6`, increases
compile time by ~25%.
* Although `-g2` increases the resident size of generated modules,
this has no effect on runtime.
Because the impact of `-g2` is minimal and the benefits of having
unconditional 100% debug information coverage (and the performance
improvement as well) are major, this commit removes `-Og` and changes
the defaults to `-O6 -g2`.
We'll have our cake and eat it too!
|
||
|---|---|---|
| .. | ||
| cxxrtl.h | ||
| cxxrtl_backend.cc | ||
| cxxrtl_capi.cc | ||
| cxxrtl_capi.h | ||
| cxxrtl_vcd.h | ||
| cxxrtl_vcd_capi.cc | ||
| cxxrtl_vcd_capi.h | ||
| Makefile.inc | ||