mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 01:24:10 +00:00
f0a52e3dd2
In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
33 lines
480 B
Systemverilog
33 lines
480 B
Systemverilog
module gate(x);
|
|
output reg [15:0] x;
|
|
if (1) begin : gen
|
|
integer x;
|
|
initial begin
|
|
for (integer x = 5; x < 10; x++)
|
|
if (x == 5)
|
|
gen.x = 0;
|
|
else
|
|
gen.x += 2 ** x;
|
|
x = x * 2;
|
|
end
|
|
end
|
|
initial x = gen.x;
|
|
endmodule
|
|
|
|
module gold(x);
|
|
output reg [15:0] x;
|
|
if (1) begin : gen
|
|
integer x;
|
|
integer z;
|
|
initial begin
|
|
for (z = 5; z < 10; z++)
|
|
if (z == 5)
|
|
x = 0;
|
|
else
|
|
x += 2 ** z;
|
|
x = x * 2;
|
|
end
|
|
end
|
|
initial x = gen.x;
|
|
endmodule
|