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https://github.com/YosysHQ/yosys
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331ac5285f
Right now neither `sat` nor `sim` have support for the `$check` cell. For formal verification it is a good idea to always run either async2sync or clk2fflogic which will (in a future commit) lower `$check` to `$assert`, etc. While `sim` should eventually support `$check` directly, using `async2sync` is ok for the current tests that use `sim`, so this commit also runs `async2sync` before running sim on designs containing assertions.
62 lines
783 B
Plaintext
62 lines
783 B
Plaintext
read_verilog -sv <<EOT
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module Task_Test_Top
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(
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input a,
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output reg b
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);
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task SomeTaskName(a);
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b = ~a;
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endtask
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always @*
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SomeTaskName(a);
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assert property (b == ~a);
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endmodule
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EOT
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proc
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async2sync
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sat -verify -prove-asserts
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design -reset
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read_verilog -sv <<EOT
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module Task_Test_Top
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(
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input a,
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output b, c
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);
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task SomeTaskName(x, output y, z);
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y = ~x;
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z = x;
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endtask
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always @*
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SomeTaskName(a, b, c);
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assert property (b == ~a);
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assert property (c == a);
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endmodule
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EOT
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proc
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async2sync
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sat -verify -prove-asserts
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design -reset
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logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
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read_verilog -sv <<EOT
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module Task_Test_Top
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(
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);
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task SomeTaskName(a)
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endtask
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endmodule
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EOT
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