yosys/tests/verilog/asgn_expr_not_sv_1.ys at ec8b745929cd02710b2d6a2f995b46c64ff54b75 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 01:24:10 +00:00

Zachary Snow 4edb1a1921 sv: support assignments within expressions

- Add support for assignments within expressions, e.g., `x[y++] = z;` or
  `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
  by injecting statements into the current procedural block.
- Add support for pre-increment/decrement statements, which are
  behaviorally equivalent to post-increment/decrement statements.
- Fix non-standard attribute position used for post-increment/decrement
  statements.

2023-09-05 22:27:55 -04:00

8 lines

174 B

Plaintext

Raw Blame History

 logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1
 read_verilog <<EOF
 module top;
 integer x, y;
 initial y = ++x;
 endmodule
 EOF